Digital Electronics & Logic Design

Boolean logic, combinational and sequential circuits, flip-flops, counters, memory, timing and the building blocks that eventually become a processor — plus a Verilog/HDL module and a full interview-prep and design-challenge track.

Lessons

1.1 Analog vs Digital: Continuous Signals vs Discrete Logic Levels
1.2 Binary Logic: Logic 0/1 and Active-High / Active-Low Conventions
1.3 Logic Levels: VIL, VIH, and the Undefined Region
1.4 Digital Signals: Period, Frequency, Duty Cycle, and Rise/Fall Time
2.1 Decimal Number System: Base-10 Positional Notation
2.2 Binary Number System: Base-2, Bits, MSB and LSB
2.3 Octal Number System: Base-8 and Binary Grouping in Threes
2.4 Hexadecimal Number System: Base-16 and 4-Bit Nibble Grouping
2.5 Base Conversion: Decimal, Binary, Octal, and Hexadecimal Interconversion
2.6 Binary Arithmetic: Addition, Subtraction, Multiplication, and Division
2.7 Signed Numbers: Sign-Magnitude, 1's Complement, and 2's Complement Ranges
2.8 1's Complement: Bit Inversion and the Dual-Zero Problem
2.9 Two's Complement: Representing Negative Numbers for Subtraction
2.10 BCD: Binary-Coded Decimal Encoding
2.11 Gray Code: Single-Bit-Transition Encoding
2.12 ASCII: Character Encoding as Binary Codes
2.13 Parity: Even/Odd Parity Bits for Error Detection
3.1 NOT Gate: Logical Inversion
3.2 AND Gate: All Inputs Must Be True
3.3 OR Gate: Any Input Being True Is Enough
3.4 NAND Gate: The Universal Building Block
3.5 NOR Gate: The Other Universal Building Block
3.6 XOR Gate: Detecting Difference
3.7 XNOR Gate: Detecting Equality
3.8 Universal Gates: Building Everything from NAND or NOR Alone
4.1 Boolean Variables and Expressions
4.2 Boolean Laws: The Algebraic Identities That Simplify Circuits
4.3 De Morgan's Laws: Pushing a Complement Through AND/OR
4.4 SOP: Sum of Products
4.5 POS: Product of Sums
4.6 Minterms: Numbering the Rows Where a Function Is True
4.7 Maxterms: Numbering the Rows Where a Function Is False
4.8 Canonical Forms: Expanding Every Minterm to Full Width
4.9 Boolean Simplification: Reducing an Expression Without Changing Its Function
5.1 K-map Fundamentals: Adjacency, Gray Code, and Prime Implicants
5.2 2-Variable K-map: Cell Arrangement, SOP and POS Minimization
5.3 3-Variable K-map: 8 Cells, Gray-Code Columns, and Pair/Quad/Octet Grouping
5.4 4-Variable K-map: 16 Cells, Wrap-Around Groups, and Essential Groups
5.5 Don't-Care Conditions: Using Unspecified Inputs to Simplify Further
6.1 Combinational Circuit: Output as a Pure Function of Current Inputs
6.2 Half Adder: Adding Two Single Bits
6.3 Full Adder: Adding Two Bits Plus an Incoming Carry
6.4 Half Subtractor: Subtracting One Bit From Another
6.5 Full Subtractor: Subtracting With an Incoming Borrow
6.6 Parallel Adder: Chaining Full Adders for Multi-Bit Addition
6.7 Carry Look-Ahead Adder: Generate, Propagate, and Faster Carries
6.8 Magnitude Comparator: Determining A > B, A = B, A < B
6.9 Multiplexer: Selecting One of Many Inputs
6.10 Demultiplexer: Routing One Input to a Selected Output
6.11 Encoder: Converting One Active Input Into a Binary Code
6.12 Priority Encoder: Resolving Multiple Simultaneously Active Inputs
6.13 Decoder: Converting a Binary Code Into One-of-Many Outputs
7.1 Combinational vs Sequential Logic: Adding Memory to Circuits
7.2 Clock: Period, Frequency, Duty Cycle, and Edge Triggering
7.3 Latch: Level-Sensitive Storage and the Transparent Phase
7.4 Flip-Flop: Edge-Triggered Storage, State, Set, and Reset
7.5 Setup Time: The Data-Stability Window Before the Clock Edge
7.6 Hold Time: Why Data Must Stay Stable After the Clock Edge
7.7 Propagation Delay: Why a Logically Correct Circuit Can Still Fail Timing
7.8 Metastability: Crossing Clock Domains Safely
8.1 SR Flip-Flop: Set-Reset Storage and Its Forbidden State
8.2 JK Flip-Flop: Solving the SR Forbidden State
8.3 D Flip-Flop: The Universal Data-Register Element
8.4 T Flip-Flop: Toggle Storage and Frequency Division
8.5 Master-Slave Flip-Flop: Two Stages, One Controlled Transfer
8.6 Flip-Flop Conversion: Excitation Tables and Building One Type from Another
9.1 Register Fundamentals
9.2 SISO: Serial-In Serial-Out Shift Register
9.3 SIPO: Serial-In Parallel-Out Shift Register
9.4 PISO: Parallel-In Serial-Out Shift Register
9.5 PIPO: Parallel-In Parallel-Out Shift Register
9.6 Universal Shift Register
9.7 Register Applications: Buffering, Serialization, and CPU Registers
10.1 Counter Fundamentals
10.2 Asynchronous / Ripple Counter
10.3 Synchronous Counter
10.4 Up Counter
10.5 Down Counter
10.6 Up/Down Counter
10.7 Mod-N Counter
10.8 Ring Counter
10.9 Johnson Counter
11.1 ROM: Read-Only Memory and Lookup Tables
11.2 PROM: Programmable Read-Only Memory
11.3 EPROM: Erasable Programmable ROM and UV Erasure
11.4 EEPROM: Electrically Erasable Programmable ROM
11.5 Flash Memory: NAND/NOR, Block Erase, and Nonvolatile Storage
11.6 RAM: Random-Access Read/Write Memory
11.7 SRAM: Static RAM and Flip-Flop-Based Storage
11.8 DRAM: Dynamic RAM, Capacitor Cells, and Refresh
11.9 PLA: Programmable Logic Array
11.10 PAL: Programmable Array Logic
11.11 FPGA Basics: LUTs, Flip-Flops, Routing, and Configuration Memory
12.1 TTL: Transistor-Transistor Logic
12.2 CMOS: Complementary MOS Logic
12.3 Fan-In: How Many Inputs a Gate Accepts
12.4 Fan-Out: How Many Loads an Output Can Drive
12.5 Noise Margin: How Much Disturbance a Signal Can Tolerate
12.6 Propagation Delay: tPLH, tPHL, and Average tPD
12.7 Tri-State Logic: The Third State, Z
12.8 Open Collector / Open Drain: Wired Logic on Shared Lines
13.1 Timing Diagrams: Reading Signal Behavior Over Time
13.2 Clock Skew: When the Clock Arrives at Different Times
13.3 Clock Jitter: Cycle-to-Cycle Timing Variation
13.4 Race Conditions: When Signal Paths Disagree
13.5 Hazards: Static and Dynamic
13.6 Glitches: Unwanted Transient Pulses
13.7 Synchronization: Crossing Clock Domains Safely
14.1 DAC: Digital-to-Analog Converter
14.2 ADC: Analog-to-Digital Converter
14.3 ADC Resolution: How Many Codes an ADC Can Produce
14.4 Quantization: Rounding a Continuous Value to a Discrete Level
14.5 Sampling: Capturing a Continuous Signal in Time
14.6 SAR ADC: Successive Approximation Register
14.7 Flash ADC: Maximum Speed via Massive Parallelism
14.8 Dual-Slope ADC: Integration-Based, Noise-Resistant Conversion
15.1 ALU: The Arithmetic Logic Unit
15.2 Arithmetic Circuits: Adders, Subtractors, Incrementers, Decrementers, Comparators
15.3 Logic Unit: Bitwise AND, OR, XOR, NOT
15.4 Shifters: Logical, Arithmetic, and Rotate
15.5 Multipliers: Partial Products, Array Multiplication, and Signed Multiplication
15.6 Register File: CPU-Internal Storage for Operands
15.7 Datapath Basics: Connecting the CPU's Building Blocks
16.1 Verilog Basics: Modules, Ports, and Continuous Assignment
16.2 Verilog Boolean Operators: Expressing Gate Logic Directly
16.3 Gate-Level Modeling: Structural Instantiation of Hardware Primitives
16.4 Combinational RTL: Continuous Assignment and always_comb
16.5 Sequential RTL: always_ff and Clocked Storage
16.6 Blocking vs. Nonblocking Assignment: = vs. <=
16.7 Testbench Basics: Verifying a Design in Simulation
16.8 Simulation vs. Synthesis: Two Different Meanings of "Running" HDL
Tricky Problem: Simplifying F = AB + AB' + A'C
Tricky Problem: Minimizing F(A,B,C,D) = Σm(0,1,2,3,8,9,10,11) on a 4-Variable K-map
Tricky Problem: Evaluating a Full Adder for A=1, B=0, Cin=1
Tricky Problem: Representing -37 in 8-Bit Two's Complement
Tricky Problem: Designing a Mod-6 Counter and Handling Its Unused States
Tricky Problem: Implementing F(A,B,C) = Sigma-m(1,2,5,7) Using a Multiplexer
Tricky Problem: Finding the Clock Period for a 100 MHz Clock
Tricky Problem: Checking a Setup-Time Requirement (Tsetup=2ns, Data 0.5ns Early)
Tricky Problem: Number of Codes and LSB Size for a 12-Bit, 3.3V ADC
Tricky Problem: Comparator Count for an 8-Bit Flash ADC
Tricky Problem: Output Frequency of a Toggling T Flip-Flop at 20 MHz
Tricky Problem: How Many States Can a 5-Bit Binary Counter Represent?
Tricky Problem: Converting Binary 1101 to Gray Code and Back
Tricky Problem: Can Unequal Path Delays Glitch the Output Even When the Steady-State Result Is Unchanged?
Tricky Problem: Writing Synthesizable RTL for a 2:1 Multiplexer
Interview Traps: Universal Gates, XOR, and Adder Architectures
Interview Traps: K-Map Adjacency Rules and Number Representation
Interview Traps: Gray Code, Encoders, Priority Encoders, and Decoders
Interview Traps: Latches vs. Flip-Flops, Setup/Hold, and Metastability
Interview Traps: Clock-Domain Synchronizers, Ripple Counters, and Ring/Johnson Counters
Interview Traps: Memory Technologies & Storage Elements
Interview Traps: Electrical Characteristics & Signal Integrity
Interview Traps: Clock Timing & Circuit Behavior
Interview Traps: ADC/DAC & Data Conversion
Interview Traps: HDL & Verilog Semantics
Design Challenge: Build Every Logic Gate From Transistors and Relays
Design Challenge: 4-Bit ALU — Combining Everything Into a Mini CPU Building Block
Design Challenge: 4-Input Digital Lock — From Boolean Logic to Stored State
Design Challenge: Traffic Light Controller — A Complete Finite-State Machine
Design Challenge: Digital Stopwatch — Clock, Counters, Registers, and 7-Segment Display