9.3 SIPO: Serial-In Parallel-Out Shift Register
Explain how a SIPO register converts a serial bit stream into a parallel word, and identify when its parallel outputs are valid to read.
A Serial-In Parallel-Out (SIPO) register shifts data in one bit at a time, exactly like a SISO register, but brings every stage's Q output out as its own external pin, so once a full word has been shifted in, all of its bits are available simultaneously, side by side. It exists because most digital systems ultimately want to work on whole words (a byte, an address, a sample) at once, even when the data arrives over a single serial wire — SIPO is the standard circuit for turning 'one bit at a time, over time' into 'all bits at once, in space.'
Core concept: same shifting, but every stage is tapped
Internally, a SIPO register is built exactly like a SISO register — a chain of flip-flops, Q of one feeding D of the next, all sharing a common clock, with a single serial input at the front. The only structural addition is that Q0, Q1, ... Qn-1 are each routed out as separate pins, not just the final stage's output. After n clock edges, the entire n-bit word that was shifted in bit-by-bit is sitting across those n parallel outputs, ready to be read in one step by whatever logic (a bus, a latch, a CPU) needs it.
Until the shifting is complete, however, the parallel outputs do not represent a valid word — they show a mixture of newly-arrived bits and leftover bits from whatever was previously in the register. A SIPO register is therefore always used together with some notion of 'word boundary': either the receiving system counts exactly n clock pulses and only then reads the parallel outputs, or a dedicated status/strobe signal is generated to say 'a full word is now ready.'
• Same internal shift chain as SISO: Din -> FF0 -> FF1 -> ... -> FF(n-1), common clock. • Every stage's Q is also brought out as a parallel output pin (Q0..Qn-1) in addition to feeding the next stage. • The parallel outputs are only meaningful once exactly n clock edges have occurred since the last full load.
Step-by-step working and worked trace
Tracing a SIPO register is identical to tracing a SISO register — build the same clock-by-clock shift table — but the point of interest shifts from 'what appears at the single serial output' to 'what does the full row Q(n-1)..Q0 look like once n clocks have elapsed.' After exactly n clock edges from a cleared (or otherwise known) starting state, the parallel outputs hold precisely the n bits that were serially applied, in the order they were shifted in, most-recently-shifted bit at one end and first-shifted bit at the other, according to the wiring direction chosen.
Practical example and real-world application
The textbook use of SIPO is serial-to-parallel conversion — for example, a UART (Universal Asynchronous Receiver/Transmitter) receiver shifts each incoming serial bit into a SIPO register; once all 8 bits of a byte have arrived, the receiver reads Q7..Q0 in parallel and presents that byte on the CPU's data bus, effectively re-assembling a byte from a stream of individual bits that arrived one at a time over a single wire.
The most common mistake with SIPO registers is reading the parallel outputs too early — before the nth clock edge has occurred — which yields a value that is part new data and part stale data from the previous load, silently corrupting whatever downstream logic consumes it. Real interfaces avoid this by gating the read with a hardware 'word complete' signal (often an interrupt or a status flag) rather than trusting a fixed delay.
SIPO block notation
Parallel outputs are valid only after a full n-clock load — reading mid-shift returns a mixed/stale value. A separate 'load complete' or 'data ready' control signal is common practice to gate downstream reads safely.
SIPO shift register (n stages):
Din --D Q--D Q--D Q--D Q--
FF0 FF1 FF2 FF3
| | | |
Q0 Q1 Q2 Q3 <- all brought out as parallel outputs
|____|____|____|
|
CLK
After n clock edges:
Q(n-1) .. Q0 = the n bits that were serially shifted in, ready to read togetherCode Examples
Bits 1,0,1,1 were fed in serially, one per clock, and only became a complete, valid 4-bit word across Q3..Q0 once the 4th clock edge occurred — reading Q3..Q0 at, say, clock 2 would have wrongly returned a half-loaded value (0100), mixing new and stale bits. Expected result: Q3 Q2 Q1 Q0 = 1 1 0 1 (valid parallel word after 4 clocks)
The parallel outputs Q3..Q0 are only a valid 4-bit word starting from clock 4 — the exact clock count of stages.
Clock# Din Q3 Q2 Q1 Q0
0 - 0 0 0 0 (reset)
1 1 1 0 0 0
2 0 0 1 0 0
3 1 1 0 1 0
4 1 1 1 0 1 <- 4th clock: full word now sitting in Q3..Q0
Parallel read after clock 4: Q3 Q2 Q1 Q0 = 1 1 0 1SIPO: serial shift-in, parallel read-out
Data enters one bit at a time on the left; once fully shifted in, the whole word is available at once on the right.
Serial In -->[FF0]-->[FF1]-->[FF2]-->[FF3]
| | | |
Q0 Q1 Q2 Q3
\_______|_______|_______/
|
(read all 4 bits together, in parallel, once loaded)Important Rules
A SIPO register needs exactly n clock edges to load a valid n-bit parallel word from a serial stream.
All stage outputs Q0..Qn-1 are wired out as pins, unlike SISO where only the last stage's output is used.
The parallel outputs must not be trusted until a full load has completed — an explicit count or a data-ready signal should gate the read.
UART and SPI receivers
SIPO registers are the receive-side building block of nearly every serial communication peripheral: a UART RX shifts in one start bit, then 8 data bits, into a SIPO register, exposing the completed byte in parallel to the CPU bus once the stop bit confirms the frame is done; SPI and similar synchronous serial protocols use the same SIPO principle on their receive line.
Reading the parallel outputs of a SIPO register at an arbitrary time, assuming they're 'always the current word.'
Only read the parallel outputs after exactly n clock edges since the register was last cleared or fully loaded — otherwise the word is a mix of new and stale bits.
Because the SIPO register is mid-shift most of the time, its parallel outputs represent a valid, complete word only at the instants right after a full n-clock load — real designs synchronize the read with a bit counter or a hardware 'data ready' strobe.
[conceptual] What is the essential structural difference between a SISO register and a SIPO register? A. SIPO uses JK flip-flops while SISO uses D flip-flops B. SIPO brings every internal stage's output out as a separate parallel pin, while SISO only exposes the final stage's output C. SIPO does not require a clock signal D. SIPO can only shift left while SISO can only shift right
B. SIPO brings every internal stage's output out as a separate parallel pin, while SISO only exposes the final stage's output — SISO and SIPO have identical internal shifting hardware — the only difference is that SIPO also routes Q0 through Q(n-1) out as individually accessible parallel pins, so a fully-shifted-in word can be read all at once instead of only observing the single bit currently exiting the chain.
[interview] A UART receiver uses an 8-bit SIPO register. If the CPU reads the parallel outputs after only 5 of the 8 data bits have arrived, what happens? A. The register automatically pads the missing bits with zero and returns a valid partial byte B. The read returns a mixture of the 5 newly-shifted bits and 3 bits left over from the previous byte, which is invalid data unless the receiver logic explicitly accounts for it C. The clock automatically pauses until all 8 bits arrive D. SIPO registers cannot be read until manually reset
B. The read returns a mixture of the 5 newly-shifted bits and 3 bits left over from the previous byte, which is invalid data unless the receiver logic explicitly accounts for it — A SIPO register's parallel outputs simply reflect whatever is currently stored in each flip-flop — reading before a full n-clock load has completed returns a value that is part new bits and part stale bits from the prior load, which is why real UARTs only signal 'data ready' after the full frame, including all data bits, has shifted in.
Design the control logic (in words) for an 8-bit SIPO UART receiver: it should assert a single-cycle 'BYTE_READY' pulse exactly when the 8th data bit has been shifted in, so the CPU knows exactly when it's safe to read Q7..Q0.
Add a 3-bit counter that increments on each data-bit clock (reset to 0 at the start of each frame). When the counter reaches 7 (the 8th bit, 0-indexed 0..7) on the same clock edge that shifts in the final bit, assert BYTE_READY for one clock cycle; the CPU (or an interrupt handler) then reads Q7..Q0 that cycle, and the counter resets for the next frame.
You need a modulo-8 bit counter that increments once per received data bit and compares against 7 (0-indexed) or 8 (1-indexed) to generate the pulse.