9.2 SISO: Serial-In Serial-Out Shift Register

Explain how a SISO shift register moves data one bit at a time through a chain of flip-flops, and calculate how many clock pulses a given bit needs to reach the output.

A Serial-In Serial-Out (SISO) register is the simplest of the four shift-register types: data enters one bit per clock at a single serial input, is passed from flip-flop to flip-flop on every clock edge, and leaves one bit per clock at a single serial output — no parallel access to the bits in between is used. It exists because not every interface needs (or can afford) n wires for an n-bit word: a single wire carrying bits one after another, synchronized to a shared clock, is the basis of virtually all serial communication, and SISO is the register topology that implements that basic serial delay/pass-through behavior.

Core concept: a straight-through chain of flip-flops

In a SISO register, the Q output of each flip-flop is wired directly to the D input of the next flip-flop, forming a chain: Input -> FF0 -> FF1 -> FF2 -> FF3 -> Output. Every flip-flop shares the same clock. On each active clock edge, every flip-flop simultaneously copies the value at its D input to its Q output — which means the whole pattern of bits shifts one position down the chain in a single step, the newest bit entering at the front and the oldest bit falling off the back (out the serial output).

Because the only externally accessible pins are the single serial input (feeding FF0's D) and the single serial output (FF(n-1)'s Q), a SISO register behaves purely as a delay line: whatever bit sequence you feed in reappears at the output, delayed by exactly n clock periods, where n is the number of flip-flop stages.

• Input -> FF -> FF -> FF -> FF -> Output, all flip-flops sharing one clock. • Each clock edge shifts every stored bit one position toward the output. • Only two pins matter externally: serial-in and serial-out — internal Q values are not brought out as separate access points in the SISO application.

Step-by-step working: tracing bits through the chain

To trace a SISO register, build a table with one row per clock edge, columns for the bit currently being applied to the serial input, and columns for each flip-flop's Q value after that edge. Before any clocks, assume the register is cleared to all zeros. Each row's flip-flop values are simply the previous row's values shifted one position, with the new serial-input bit inserted at the front.

The key consequence of this mechanic is the spec's core tricky point: the very first bit you feed in does not appear at the serial output right away — it has to physically ripple, one clock at a time, through every intermediate flip-flop before it reaches the last stage. For an n-stage SISO register, the first input bit reaches the output only after exactly n clock edges.

Practical application and common mistake

Because a SISO register's only job is to delay a serial bit stream by a fixed number of clock periods, it's used directly as a digital delay line — for example, delaying one channel of a signal relative to another by an exact, clock-accurate number of cycles, or building simple pseudo-random / recirculating delay elements when combined with feedback.

The most common mistake is expecting immediate pass-through behavior, as if the register were just a wire. In reality the total propagation time through an n-stage SISO chain is n complete clock periods, and that delay must be budgeted for in any timing-sensitive design that uses one — for instance, if you're comparing a delayed and an undelayed copy of the same bit stream, you must resynchronize them by exactly that many clock cycles before comparing bit-for-bit.

SISO block notation

n = number of flip-flop stages = number of clock edges a bit needs to travel from Din to Dout. No intermediate Qi is exposed as an external pin in a pure SISO application — that is what SIPO adds.

SISO shift register (n stages):

  Din --D Q--D Q--D Q--D Q-- Dout
         FF0  FF1  FF2  FF3
          |____|____|____|
               |
              CLK  (common clock; one edge = one shift)

Behavior each active clock edge:
  Q0(next) = Din
  Q1(next) = Q0(current)
  Q2(next) = Q1(current)
  Q3(next) = Q2(current)
  Dout     = Q3(current)  -- the bit that just "fell off" the chain

Code Examples

Bit '1' entered at clock 1 lands in Q0, moves to Q1 at clock 2, Q2 at clock 3, and only reaches Q3 (the output) at clock 4 — four clock edges after it was entered, matching n=4 stages. Each subsequent input bit follows the same 4-clock journey, one clock behind the bit before it. Expected result: Serial output stream (from clock 4 onward): 1, 0, 1, 1, ... — same sequence as the input, delayed by 4 clocks.

The bit entered at clock 1 reaches the serial output only at clock 4 — a delay of exactly n = 4 clock periods.

Clock#   Din   Q0  Q1  Q2  Q3(=Dout)
  0       -    0   0   0   0        (reset state)
  1       1    1   0   0   0
  2       0    0   1   0   0
  3       1    1   0   1   0
  4       1    1   1   0   1   <- first input bit (1) finally appears at Dout
  5       -    -   1   1   0
  6       -    -   -   1   1
  7       -    -   -   -   1

SISO as a 4-clock-period delay line

A SISO register is functionally a shift-in / shift-out delay line, length = number of stages.

Serial In -->[FF0]-->[FF1]-->[FF2]-->[FF3]--> Serial Out
               |________|________|________|
                            |
                           CLK

Bit takes 4 clock edges to travel from Serial In to Serial Out.

Important Rules

An n-stage SISO register delays a serial bit stream by exactly n clock periods.

Only the serial-in and serial-out pins are used externally — the intermediate flip-flop outputs carry the in-transit bits but are not tapped.

Every flip-flop shifts on the same clock edge, so the entire stored pattern moves exactly one position per clock, never more, never less.

Serial delay lines and bit-serial links

SISO registers underlie any fixed-length digital delay, such as delaying a data or control signal by a known, exact number of clock cycles to align it with another path in a synchronous system, and they are the conceptual core of bit-serial communication paths inside chips and between chips, where wires are precious and data is deliberately sent one bit at a time rather than n bits in parallel.

Assuming a bit applied to the serial input appears at the serial output on the very next clock edge, regardless of register length.

The first input bit only reaches the output after n clock edges, where n is the number of flip-flop stages — it must ripple through every intermediate flip-flop first.

This is exactly the spec's tricky point for SISO: intermediate stages are real storage elements the data must pass through one clock at a time, not a transparent path — a 4-stage SISO register always has a 4-clock latency from input to output.

[tricky-problem] In a 5-stage SISO shift register, why don't all five stored bits appear at the serial output at the same time as they were entered? A. Because the flip-flops are not all connected to the same clock B. Because data must ripple through each flip-flop one clock edge at a time — a bit fed in at clock k only reaches the final stage's output at clock k + 5 C. Because SISO registers use asynchronous, not synchronous, flip-flops D. Because the register's clear input must be pulsed between every bit

B. Because data must ripple through each flip-flop one clock edge at a time — a bit fed in at clock k only reaches the final stage's output at clock k + 5 — Every stage in a SISO chain is a real flip-flop the data must pass through, one position per clock edge. With 5 stages, a bit needs exactly 5 clock edges to travel from the serial input to the serial output — this ripple-through-the-chain latency is the defining, and most commonly misunderstood, behavior of a shift register.

[interview] What is the primary practical use of a SISO shift register, given that it exposes no parallel access to its stored bits? A. Storing a value for random access by address, like RAM B. Acting as a fixed-length, clock-accurate serial delay line for a bit stream C. Performing binary addition of two numbers D. Generating a clock signal

B. Acting as a fixed-length, clock-accurate serial delay line for a bit stream — Since SISO offers only a serial-in and serial-out pin, its natural role is delaying a serial bit stream by a known number of clock cycles — it cannot be used for random access (that needs parallel-out) or for arithmetic (that needs adder logic), but it is exactly the right tool for a precise digital delay line.

A 6-stage SISO register is fed the serial bit stream 1,1,0,1,0,0,1,1,... starting at clock 1. On which clock edge does the third input bit (the third '1' counting duplicates, i.e. the bit fed at clock 3, which is '0') appear at the output, and what is that bit's value?

n = 6, so the bit fed at clock 3 (value 0) appears at the output at clock 3 + 6 = clock 9.

Every bit fed at clock k appears at the output at clock k + n, where n is the number of stages.