Interview Traps: Clock Timing & Circuit Behavior

Cleanly separate the two most confused pairs of timing/circuit-behavior terms — clock skew vs. clock jitter, and hazard vs. glitch — with precise definitions and a worked hazard example, instead of the interchangeable, hand-wavy usage that fails follow-up questions.

This cluster exists almost entirely to catch candidates who use two terms interchangeably when they mean genuinely different things. Skew and jitter are both 'clock timing isn't perfect,' and hazard and glitch are both 'the output does something wrong briefly' — but interviewers ask these specifically because sloppy, interchangeable answers reveal a shallow mental model, while a precise answer (spatial vs. temporal; potential vs. event) signals real understanding of timing analysis.

What is clock skew?

Clock skew is the difference in arrival time of the same clock edge at two different sequential elements (flip-flops) in a design, caused by unequal delay along the clock distribution network reaching each one — different wire lengths, different numbers of buffers, different loading on each branch of the clock tree. It is fundamentally a spatial phenomenon: at one specific moment (one particular rising edge of the clock), the edge shows up at flip-flop A at a slightly different time than it shows up at flip-flop B, because the physical paths from the clock source to A and to B are not identical.

Skew matters directly for setup and hold timing analysis: positive skew (the receiving flip-flop's clock arrives later than the launching flip-flop's) effectively gives a signal more time to propagate before the next edge captures it, which can help setup timing but hurts hold timing (and vice versa for negative skew). Chip designers spend real engineering effort building balanced clock trees (e.g., H-trees) specifically to minimize skew across a large die.

What is clock jitter?

Clock jitter is the short-term variation in a clock signal's period or edge position at a single point in the circuit, measured over successive cycles — it is a temporal phenomenon, not a spatial one. Even watching only one flip-flop's clock input, its actual rising edges will not land at perfectly uniform intervals; they wobble slightly cycle to cycle due to noise sources like power supply variation, thermal noise in the clock generator (often a PLL), and crosstalk. Jitter is typically characterized statistically (e.g., peak-to-peak or RMS jitter, in picoseconds).

The essential distinction from skew: skew compares the SAME edge arriving at DIFFERENT physical locations at essentially the same time; jitter compares DIFFERENT edges (successive cycles) at the SAME physical location over time. Confusing the two is the single most common trap in this pair, and interviewers will often ask a candidate to define both back-to-back specifically to see if the definitions get swapped or blurred together under pressure.

What is a hazard?

A hazard is a property of a circuit's logic structure — a potential for the output to glitch. It arises when a single input change should logically leave the output unchanged (or change it cleanly once), but the change propagates to the output gate through two or more different logic paths with different propagation delays. Because those paths don't settle at exactly the same instant, the gate combining them can momentarily see an inconsistent combination of its inputs and produce a brief incorrect pulse before everything settles to the correct final value.

Critically, a hazard is about the circuit's design/topology — it exists (or doesn't) based on how the logic is structured, independent of whether any particular test vector ever actually triggers it. A circuit 'has a static-1 hazard for this input transition' is a statement about potential behavior, verifiable by examining the K-map/circuit paths, not a statement that a glitch was observed on an oscilloscope.

What is a glitch?

A glitch is the actual event: an observed, unwanted, momentary transition in a signal — the output dipping to 0 and back (or spiking to 1 and back) for a brief instant when it should have stayed constant — caused when a hazard is triggered by a real input transition and the differing path delays actually produce the transient pulse in practice.

The trap is using 'hazard' and 'glitch' interchangeably, most commonly by describing the transient pulse itself as 'the hazard.' The precise relationship is: a hazard is the underlying design condition (potential for a problem, identifiable statically from the logic), and a glitch is what you actually see on a waveform when that potential is realized by a specific input transition and real circuit delays. A well-designed circuit can have zero hazards (verified on paper) and therefore will never glitch on that signal path, no matter what input sequence is applied — which is exactly why hazard analysis is done during design, before any simulation waveform exists.

Code Examples

This is the canonical static-1 hazard: the K-map grouping is logically correct (F really does equal 1 in both the before and after states) but the GATE-LEVEL implementation has two different-delay paths converging on the output OR gate, and when one path turns off slightly before the other turns on, the output dips momentarily. The fix is a redundant term that overlaps the boundary between the two original groups, so at least one term is always asserted during the transition.

Adding the redundant term A*C removes the hazard by ensuring no instant exists where every term is simultaneously 0.

F = A*B' + B*C
Hold A = 1, C = 1, let B transition from 1 to 0:
  Before (B=1): F = A*B' + B*C = 1*0 + 1*1 = 1
  After  (B=0): F = A*B' + B*C = 1*1 + 0*1 = 1
  Logically F should stay 1 throughout the transition.

But: term A*B' turns ON as B falls (needs B' to rise from 0->1,
     delayed by the inverter producing B')
     term B*C turns OFF as B falls (immediately, no inverter delay)
If B*C switches off BEFORE A*B' switches on (inverter delay on B'),
there is a brief instant where BOTH terms are 0 -> F glitches to 0
before A*B' catches up and restores F to 1.

Fix: add the redundant consensus term A*C (covers the K-map cells
adjacent across the B boundary), giving F = A*B' + B*C + A*C.
A*C stays 1 throughout the whole transition (A=1, C=1 never change),
holding the output up while the other two terms switch.

Skew (spatial, same edge) vs. Jitter (temporal, same point) vs. Hazard -> Glitch

Skew and jitter are both about clock timing but differ in spatial-vs-temporal axis; hazard and glitch are both about output pulses but differ in potential-vs-event.

SKEW (same clock edge, two locations, one moment):
  clk at FF_A: ______/‾‾‾‾\______
  clk at FF_B: ________/‾‾‾‾\____   <- arrives later: this gap is SKEW

JITTER (one location, many cycles):
  clk at FF_A, cycle 1: __/‾‾\____
  clk at FF_A, cycle 2: ___/‾‾\___   <- edge wobbles cycle to cycle: this is JITTER
  clk at FF_A, cycle 3: __/‾‾\____

HAZARD -> GLITCH (single input change, two unequal-delay paths into one gate):
  input B changes:  ‾‾‾‾‾\_____________
  path1 (fast):     _____/‾‾‾‾‾‾‾‾‾‾‾‾\_
  path2 (slow):     ‾‾‾‾‾‾‾\___________/
  OUTPUT (should stay 1): ‾‾‾\_/‾‾‾‾‾‾‾‾‾  <- brief dip = the GLITCH;
                                              the circuit's unequal-delay
                                              structure that made this
                                              possible is the HAZARD

Why this distinction drives real timing closure work

Clock tree synthesis in ASIC/FPGA physical design exists specifically to control skew — engineers build balanced H-tree or mesh clock distribution networks so every flip-flop sees the clock edge at nearly the same time, because uncontrolled skew directly eats into setup/hold timing margins across the whole chip. Jitter is budgeted separately in high-speed serial links (SERDES, PCIe, DDR interfaces), where PLL/clock-generator jitter directly reduces the usable data eye at multi-gigabit rates, regardless of how well-balanced the clock tree is. Hazard-free logic design matters most in asynchronous circuits and control logic (e.g., an asynchronous reset or bus arbiter) where a glitch on a control signal can cause a real, incorrect state transition rather than just being masked by the next clock edge the way it usually is in purely synchronous datapaths.

Clock skew is when the clock period varies slightly from cycle to cycle.

That describes clock jitter (temporal variation at one point, cycle to cycle). Clock skew is the difference in arrival time of the SAME clock edge at DIFFERENT physical locations (different flip-flops) in the circuit.

Skew and jitter are swapped constantly because both sound like 'the clock isn't perfectly regular.' The discriminating question to ask is: are we comparing one edge across different points in space (skew), or many edges over time at one point (jitter)?

What is the key difference between clock skew and clock jitter? A. They are two names for the same phenomenon. B. Skew is the variation of the clock's period over many cycles at one point; jitter is the difference in arrival time of the same edge at two different points. C. Skew is the difference in arrival time of the same clock edge at different physical locations (a spatial difference); jitter is the cycle-to-cycle variation of the clock edge's timing at a single location (a temporal variation). D. Skew only matters for DRAM; jitter only matters for SRAM.

C. Skew is the difference in arrival time of the same clock edge at different physical locations (a spatial difference); jitter is the cycle-to-cycle variation of the clock edge's timing at a single location (a temporal variation). — Skew compares the same edge across different flip-flops at essentially one instant (spatial). Jitter compares successive edges at one point over time (temporal). Both affect timing margins but come from different physical causes and are analyzed differently.

What is the precise relationship between a hazard and a glitch? A. They are interchangeable terms for the same waveform event. B. A hazard is a design-level potential for a bad output transition due to unequal-delay paths converging on a gate; a glitch is the actual transient pulse observed when a real input change triggers that potential. C. A glitch is a permanent output error; a hazard is a temporary one. D. A hazard only occurs in sequential circuits; a glitch only occurs in combinational circuits.

B. A hazard is a design-level potential for a bad output transition due to unequal-delay paths converging on a gate; a glitch is the actual transient pulse observed when a real input change triggers that potential. — Hazard = static property of the logic structure, identifiable from the K-map/schematic without ever simulating an input transition. Glitch = the dynamic event that appears on a waveform when an actual input transition exercises a hazard.

For F = A·B' + B·C with A=1 and C=1 held constant, why does F momentarily glitch to 0 when B transitions? A. Because F is logically supposed to become 0 during this transition. B. Because the term B·C turns off as soon as B falls, while the term A·B' turns on only after B' rises through an inverter delay — for a brief instant both terms can be 0 even though F should stay 1 throughout. C. Because A and C are also changing at the same time as B. D. Because the OR gate combining the two terms is faulty.

B. Because the term B·C turns off as soon as B falls, while the term A·B' turns on only after B' rises through an inverter delay — for a brief instant both terms can be 0 even though F should stay 1 throughout. — F is logically 1 both before and after the B transition, but the two AND terms don't hand off instantaneously — one switches off before the other (delayed by an inverter) switches on, producing a brief dip. Adding the redundant term A·C, which doesn't depend on B, removes the hazard.

A balanced H-tree clock distribution network is built primarily to minimize which of the following? A. Clock jitter B. Clock skew C. Static hazards D. Quantization error

B. Clock skew — An H-tree equalizes the physical path length (and therefore delay) from the clock source to every flip-flop, which directly targets clock skew (spatial arrival-time differences), not jitter (which is a property of the clock source's own timing stability, not the distribution network's path-length balance).

For F = A·B' + B·C, identify which single-variable transition (holding the other two constant) produces a static-1 hazard, and state the redundant product term that eliminates it. Then explain in one sentence why a fully synchronous design (every signal sampled by a flip-flop on a clock edge) is often tolerant of this kind of glitch even without adding the redundant term.

The B transition (with A=1, C=1 held constant) produces the static-1 hazard, as shown in the worked example; adding A·C removes it. A synchronous design is often tolerant of it because the flip-flop only samples the signal at the clock edge — as long as the glitch settles out well before the next active edge (within the setup time margin), the transient incorrect value is never captured, though this tolerance disappears for asynchronous inputs like resets or clock-enables that aren't themselves re-synchronized.

Look at which literal is complemented in one term but not the other, and check whether the transition of that variable causes one term to switch off while the other switches on through an inverter delay.