11.8 DRAM: Dynamic RAM, Capacitor Cells, and Refresh

Explain why DRAM cells must be periodically refreshed, how a memory controller manages this, and why DRAM achieves much higher density than SRAM.

Dynamic RAM (DRAM) stores each bit of data as an electrical charge on a tiny capacitor, accessed through a single transistor — the classic one-transistor, one-capacitor (1T1C) DRAM cell. This is dramatically simpler and smaller than SRAM's six-transistor flip-flop cell, which lets DRAM pack far more bits into the same silicon area, making it the dominant technology for a computer's main memory, where capacity matters enormously. The trade-off is that a capacitor is not a perfect charge reservoir: leakage currents cause the stored charge to drain away over a period of milliseconds, so unlike SRAM's self-sustaining feedback latch, a DRAM cell's data would simply fade away and be lost if left alone. To prevent this, DRAM requires refresh: a memory controller must periodically read out and rewrite every cell's charge before it decays past the point of reliable detection, a continuous background maintenance process that gives DRAM its name — 'dynamic' precisely because the stored charge is not static and must be actively renewed.

Core concept: capacitor-based storage and why refresh is mandatory

A DRAM cell's single capacitor holds charge (or the absence of it) to represent a stored bit: a charged capacitor represents one logic state, a discharged one the other. Reading a DRAM cell is inherently destructive to the stored charge — sensing the tiny capacitor voltage through the access transistor disturbs it — so every DRAM read cycle must be followed internally by a rewrite of the sensed value back into the same cell, restoring its charge to a full level. This destructive-read/restore behavior is fundamentally different from SRAM, where reading merely senses an already self-sustaining latch without disturbing it.

Even without being read, however, a DRAM capacitor's charge slowly leaks away through unavoidable parasitic leakage paths in the silicon. If nothing were done about this, a cell's data would become unreliable within tens of milliseconds. The memory controller therefore issues periodic refresh commands — cycling through every row in the array on a fixed schedule (a common industry figure is refreshing the entire array roughly every 64 milliseconds, though exact timing is technology- and part-specific) — reading and immediately rewriting each row to restore full charge before it decays too far to be read correctly.

• Capacitor-based storage: each bit held as charge (or its absence) on a tiny 1T1C cell • Refresh: periodic read-and-rewrite of every row, required to counteract charge leakage • Density: the simple 1T1C cell is far smaller than SRAM's 6T cell, giving much higher bits-per-area • Memory controller concepts: refresh scheduling, row activation, and timing are managed by a dedicated DRAM controller, not by the CPU core directly

Step-by-step: DRAM access with the refresh obligation in the background

Access: the memory controller asserts a row address, which activates an entire row of cells, driving their capacitor charge onto that row's bit lines; sense amplifiers detect the (very small) resulting voltage and restore it to a full logic level, which conveniently both produces the read data and refreshes that row's charge at the same time. A column address then selects which bit(s) within the activated row are delivered as the actual read result, and the row is typically closed (precharged) afterward to prepare for the next access.

Refresh (independent of any CPU-requested access): the controller periodically issues refresh commands that step through every row in the array in turn, performing exactly the same activate/sense/restore sequence as a read, whether or not any CPU access happens to touch that row — this is what keeps data valid in rows that the CPU has not recently accessed on its own.

Tricky concept: what 'dynamic' does and does not mean

The name 'dynamic' refers specifically to the need to refresh the stored charge — it has nothing to do with how DRAM is addressed or accessed. DRAM is still random-access memory: any row/column address can be reached directly, exactly like SRAM, and DRAM access is not sequential in the sense of tape or shift-register storage. Students sometimes mistakenly assume 'dynamic' implies some kind of sequential or unpredictable access pattern; it does not — it purely describes the charge-refresh requirement of the storage cell itself.

This is also why DRAM's density advantage over SRAM comes bundled with real system-level cost: the memory controller must dedicate a portion of every access cycle's bandwidth to refresh traffic, and refresh commands compete with normal read/write traffic for the same array — a scheduling and performance concern that SRAM, with no refresh requirement at all, never has to manage.

DRAM cell and refresh notation

1T1C DRAM cell:
  1 access transistor + 1 storage capacitor  → simplest possible RAM cell

Refresh requirement:
  Charge leaks over time  →  entire array must be refreshed periodically
  Typical industry figure: full-array refresh interval ≈ 64 ms (technology-dependent)

Read behavior: DESTRUCTIVE — sensing disturbs the charge, so every read
implicitly requires a restore (rewrite) of the sensed value back into the cell.

Code Examples

This shows why refresh must happen regardless of whether the CPU is actively using a given row: without the controller's background refresh sweeps, data in rows the CPU is not currently touching would simply decay and be lost.

DRAM's data survives only because the memory controller refreshes every row on a fixed schedule, whether or not the CPU is using it.

Row 12 written with data at t = 0 ms, then never explicitly read/written again
by the CPU for the next 200 ms.

Without refresh:
  t ≈ 60-100 ms: leakage has drained enough charge that the stored bit
                 becomes unreliable or unreadable.

With the memory controller's periodic refresh (every ~64 ms):
  t = 0 ms:   Row 12 written
  t = 64 ms:  Controller refresh cycle reaches Row 12 → sense + restore charge
  t = 128 ms: Controller refresh cycle reaches Row 12 again → sense + restore
  t = 200 ms: CPU finally reads Row 12 → data is still correct,
              thanks to the two refresh cycles in between

DRAM 1T1C cell (conceptual)

A single transistor gates access to a single capacitor — far simpler than SRAM's 6-transistor bistable cell, but the capacitor's charge leaks and must be refreshed.

Word Line (row select)
                        │
                   ┌────▼────┐
   Bit Line ────────┤ access │
                    │  Tx    │
                    └────┬────┘
                         │
                       ──┴──
                       ─────   ← storage capacitor
                       ──┬──   (charge = one logic state,
                         │      discharged = the other)
                        GND

Important Rules

DRAM stores each bit as capacitor charge, accessed via a single transistor (1T1C).

Capacitor charge leaks over time and must be periodically refreshed by the memory controller.

'Dynamic' refers to the refresh requirement, not to sequential or unpredictable access — DRAM is still random access.

DRAM reads are destructive to the sensed charge and require an internal restore as part of the read cycle.

DRAM's simple cell gives much higher density than SRAM, at the cost of refresh overhead and somewhat slower access.

Where DRAM is used

DRAM (in forms such as DDR4/DDR5 SDRAM) is the standard technology for a computer's main system memory, where high capacity at low cost per bit matters far more than the absolute lowest possible latency — the gap is bridged by SRAM caches sitting between the CPU and DRAM main memory.

Assuming 'dynamic' in DRAM means the memory is accessed sequentially or unpredictably.

'Dynamic' refers only to the need to refresh leaking capacitor charge; DRAM remains genuinely random-access, exactly like SRAM.

This is the tricky point called out directly in the source material: dynamic describes the refresh requirement of the storage mechanism, not the addressing/access pattern, which stays random access.

[tricky] The source material warns: "'Dynamic' refers to the need to refresh stored charge; it does not mean that access is sequential." What misconception does this correct? A. That DRAM cannot be used for main memory B. That the term 'dynamic' implies DRAM must be accessed in sequential order, like a shift register or tape, when in fact DRAM is still random-access memory and 'dynamic' only describes the refresh requirement C. That DRAM cells use flip-flops instead of capacitors D. That DRAM refresh happens only once at power-on

B. That the term 'dynamic' implies DRAM must be accessed in sequential order, like a shift register or tape, when in fact DRAM is still random-access memory and 'dynamic' only describes the refresh requirement — The word 'dynamic' is easy to misread as describing the access pattern, but it strictly refers to the storage mechanism: capacitor charge that decays and must be refreshed. DRAM's addressing remains fully random-access, exactly like SRAM or ROM — any row/column can be reached directly.

[interview] Why does DRAM achieve much higher storage density than SRAM at the same process technology? A. DRAM cells run at a lower voltage B. DRAM's cell needs only one transistor and one capacitor (1T1C), far fewer components than SRAM's six-transistor bistable latch, so many more DRAM cells fit in the same silicon area C. DRAM does not require sense amplifiers D. DRAM cells do not need an access transistor

B. DRAM's cell needs only one transistor and one capacitor (1T1C), far fewer components than SRAM's six-transistor bistable latch, so many more DRAM cells fit in the same silicon area — The component count directly drives area: DRAM's minimal 1T1C cell is far smaller than SRAM's 6T cross-coupled-latch cell, so a DRAM array packs many more bits into the same die area — the direct cause of DRAM's density and cost-per-bit advantage over SRAM, at the cost of needing refresh and being somewhat slower to access.

Explain, step by step, why a DRAM row that is read very frequently by the CPU still needs the memory controller's separate, scheduled refresh commands rather than relying on those frequent reads alone to keep its data valid.

A read does restore charge to the row it touches (since sensing includes a restore step), so a frequently-read row is, incidentally, also being kept refreshed by its own reads. But the memory controller cannot assume this for the array as a whole: most rows in a large DRAM array are not read anywhere near often enough by normal program activity to be refreshed purely as a side effect, and the controller has no reliable way to know in advance which rows will or won't be accessed soon. Scheduled refresh guarantees every row — accessed or not — is restored on a fixed interval (about every 64 ms), which is the only way to guarantee correctness for the entire array regardless of the access pattern any particular program happens to produce.

Think about whether every row in the array is guaranteed to be read often enough, and whether reads and refresh serve the same underlying electrical purpose.