11.7 SRAM: Static RAM and Flip-Flop-Based Storage

Explain how SRAM stores each bit in a flip-flop-style latch, why it needs no refresh, and why that comes at a real area/cost trade-off versus DRAM.

Static RAM (SRAM) stores each bit of data in a small flip-flop-style bistable latch circuit built from a handful of transistors — commonly six in the classic 6-transistor (6T) SRAM cell design. As long as power is supplied to the cell, the cross-coupled transistor pair holds its logic state indefinitely through positive feedback, with no need to periodically refresh or rewrite the stored value. This is exactly what the name 'static' refers to: the data stays put on its own, statically, for as long as power is applied, in direct contrast to DRAM's capacitor-based cells (covered next), which slowly lose their charge and must be actively refreshed at regular intervals to avoid data loss. SRAM's flip-flop-based design gives it very fast access times and simple control, which is why it is the technology of choice for CPU caches and register files, but each SRAM cell needs more transistors — and therefore more silicon area — than a DRAM cell, which limits how much SRAM can be economically packed onto a chip.

Core concept: flip-flop-based storage, no refresh required

Each SRAM bit cell is essentially the same cross-coupled-inverter bistable circuit studied as the basic latch in sequential logic fundamentals: two inverters connected so that each one's output feeds the other's input, creating two stable states that reinforce themselves through positive feedback. Once set to a state (0 or 1), the cell will hold that state indefinitely as long as power remains applied — there is no decay mechanism internal to the cell that requires periodic intervention.

Access transistors connect this bistable pair to the bit lines, controlled by the word line from the row decoder, exactly mirroring the address-decoder access pattern used throughout the ROM/RAM family: an address selects a row (word line), which enables that row's cells onto the column bit lines for reading or writing.

• Flip-flop-based storage: each bit is a small bistable latch (commonly a 6-transistor cell) • No refresh requirement: data is retained as long as power is applied, with no periodic rewrite needed • Speed: SRAM access times are very fast because reading is simply sensing the latch's current state • Area trade-off: more transistors per bit than DRAM means lower density and higher cost per bit at a given process node

Step-by-step: reading and writing an SRAM cell

Read: the row decoder asserts the target word line, which turns on that row's access transistors, connecting each cell's stored state onto a pair of complementary bit lines; a sense amplifier detects the small voltage difference between the bit lines and resolves it into a clean digital 0 or 1 on the data output — a fast operation because the latch is already actively driving its state, requiring only sensing, not charge restoration.

Write: the word line is again asserted to enable the access transistors, but this time the bit lines are driven strongly by external write circuitry to the desired new values, forcing the cross-coupled latch to flip into the new state by overpowering its own feedback; once the word line is deasserted, the latch holds the newly written state on its own, exactly as it held the previous one.

Why the speed/area trade-off matters in real designs

Because SRAM requires no refresh cycles and no wait for capacitor charge/discharge, its access latency is dominated purely by wire and transistor switching delay, making it the fastest common RAM technology — which is exactly why it is used for CPU L1/L2/L3 caches and register files, where every nanosecond of access latency directly limits processor performance.

The cost of that speed is area: a 6-transistor SRAM cell occupies significantly more silicon than a single-transistor DRAM cell (see the DRAM topic), so for a fixed die area, an SRAM array holds far fewer bits than a DRAM array at the same process technology. This is the fundamental reason computer systems use a mix of both: a small amount of fast, expensive SRAM as cache, backed by a much larger amount of slower, cheaper DRAM as main memory.

SRAM cell notation

Classic 6T SRAM cell:
  2 cross-coupled inverters  → the bistable storage element (the "flip-flop")
  2 access transistors       → connect the cell to the bit-line pair, gated by word line

Retention condition:  Data held indefinitely WHILE POWER IS APPLIED — no refresh needed
Loss condition:       Data lost only when power is removed (volatile, like all standard RAM)

Code Examples

The point is not that SRAM is nonvolatile (it is still volatile RAM, like all RAM covered here) — the point is that, while powered, SRAM needs no active maintenance to keep its stored bit correct, unlike DRAM.

SRAM's bistable latch holds its state on its own, indefinitely, as long as power stays on.

t = 0 ms:    Cell written with logic 1 (word line pulsed, bit lines forced to '1' state)
t = 1 ms:    Read back → 1   (no refresh performed in between)
t = 1000 ms: Read back → 1   (still no refresh performed — state held by feedback alone)
t = 1000 ms + power removed: Cell contents lost (volatility, not a refresh failure)

Compare to DRAM: a DRAM cell left this long without refresh pulses would
have already lost its charge and returned unreliable data well before 1000 ms.

SRAM 6T cell (conceptual)

Two cross-coupled inverters hold Q/Q_bar in a stable state via positive feedback; two access transistors connect the cell to the bit-line pair for read/write.

Word Line (row select)
                        │
        ┌───────────────┼───────────────┐
        │               │               │
   BitLine ──┤ access ├──●────●──┤ access ├── BitLine_bar
   (BL)         Tx    Q │    │ Q_bar   Tx        (BL_bar)
                        │    │
                  ┌─────▼────▼─────┐
                  │  Cross-coupled  │
                  │    inverters    │   ← the bistable storage element
                  │   (2 inverters) │
                  └─────────────────┘

Important Rules

Each SRAM bit is stored in a bistable flip-flop-style latch, commonly a 6-transistor cell.

SRAM needs no periodic refresh — positive feedback holds the state as long as power is applied.

SRAM is fast because reads only require sensing an already-driven state, not restoring charge.

SRAM's transistor count per bit trades off against density: SRAM is less dense (and costs more per bit) than DRAM.

Where SRAM is used

SRAM is used wherever access speed matters more than density or cost per bit: CPU L1/L2/L3 caches, register files, FPGA block RAM, and small high-speed buffers inside networking and storage controllers, all rely on SRAM's fast, refresh-free access.

Believing 'static' in SRAM means the data survives power loss (nonvolatile).

'Static' describes the absence of a refresh requirement while powered, not nonvolatility — SRAM is still volatile RAM and loses its contents when power is removed.

This is one of the most common misreadings of the term: static/dynamic in SRAM/DRAM refers to whether the stored charge needs active refreshing, not to volatility, which both share.

[tricky] Why does SRAM require no refresh operation, unlike DRAM? A. Because SRAM is nonvolatile B. Because each SRAM cell is a bistable flip-flop-style latch held in its state by positive feedback, as opposed to a capacitor that leaks charge over time C. Because SRAM cells are read faster than they can leak D. Because SRAM uses UV light to maintain charge

B. Because each SRAM cell is a bistable flip-flop-style latch held in its state by positive feedback, as opposed to a capacitor that leaks charge over time — SRAM's cross-coupled-inverter cell actively reinforces its own stored state through positive feedback as long as power is applied, so there is no decay to counteract. DRAM's single-capacitor cell has no such feedback and must be periodically refreshed before its charge leaks away.

[interview] Why isn't SRAM used for a computer's entire main memory, given that it is faster than DRAM? A. SRAM cannot be manufactured at large capacities at all B. SRAM's larger per-bit transistor count (commonly 6T) makes it significantly less dense and more expensive per bit than DRAM's simpler cell, so an all-SRAM main memory of typical gigabyte-scale capacity would be prohibitively large and costly C. SRAM loses data faster than DRAM D. SRAM cannot be randomly addressed

B. SRAM's larger per-bit transistor count (commonly 6T) makes it significantly less dense and more expensive per bit than DRAM's simpler cell, so an all-SRAM main memory of typical gigabyte-scale capacity would be prohibitively large and costly — This is the direct speed/area trade-off the course material calls out: SRAM's flip-flop-based cell needs more transistors than DRAM's capacitor-based cell, so for a fixed die area SRAM stores far fewer bits — making gigabyte-scale all-SRAM main memory economically impractical, which is why systems use a small SRAM cache backed by much larger DRAM main memory.

A CPU designer must choose between SRAM and DRAM for a new 32 KB L1 cache that must respond within one clock cycle at multi-gigahertz speed. Justify the choice using SRAM's speed/area trade-off.

SRAM is the correct choice. An L1 cache must respond within a single CPU clock cycle at multi-gigahertz frequencies, which only SRAM's refresh-free, feedback-held bistable cells can reliably deliver — DRAM's charge-restoration and periodic refresh overhead make it far too slow for this role. Although SRAM's 6-transistor cells are much less area-efficient than DRAM's, the target capacity here (32 KB) is small enough that the extra silicon area is an acceptable cost for the speed gained; DRAM's density advantage matters far more at multi-gigabyte main-memory scales than at kilobyte-scale caches.

Weigh access latency requirements against the relatively small capacity needed (32 KB is tiny compared to typical DRAM main memory sizes).