10.6 Up/Down Counter
Explain how a single counter circuit supports both counting directions via a mode-select input, derive its combined excitation logic, and identify the synchronization hazard direction changes can create.
An up/down counter combines both the up-counting and down-counting next-state rules into a single circuit, selected on the fly by a direction-control input — typically named UP, or UP/DOWN — so the same hardware can count forward or backward depending on what that control line says at each clock edge. It exists because many real applications need to count in both directions depending on circumstance: an elevator counting floors up or down depending on travel direction, a rotary encoder counting position forward or backward depending on which way it's turned, or a digital volume control incrementing or decrementing depending on which button is pressed.
Core concept: a mux selects between carry and borrow logic per stage
Per the spec's typical convention (the exact active level is implementation-defined and should be confirmed against a specific part's datasheet), UP = 1 selects up-counting and UP = 0 selects down-counting. Structurally, each stage's excitation logic becomes a small multiplexer choosing between the up-counter's carry-toggle condition (AND of lower bits) and the down-counter's borrow-toggle condition (AND of complemented lower bits), based on the UP control line, before that result feeds the flip-flop's toggle input.
For a synchronous bidirectional counter built from T flip-flops: T0 = 1 regardless of direction (the LSB always toggles on every clock, whichever way the counter is running); T1 = (UP AND Q0) OR (NOT UP AND NOT Q0); and in general, Tk = (UP AND [AND of lower bits]) OR (NOT UP AND [AND of complemented lower bits]) — a direct combination of the up counter's and down counter's individual excitation equations, gated by the direction control.
• One UP/DOWN control line selects, per stage, between the carry-toggle (up) condition and the borrow-toggle (down) condition. • The LSB toggles on every clock regardless of direction; only the higher bits' toggle condition actually depends on UP. • Common commercial ICs (e.g., 74LS191, 74LS193) implement this either with a single direction pin or with separate UP-clock and DOWN-clock inputs, depending on the family.
Step-by-step working: reversing direction mid-sequence
Because direction is just another input to the same excitation logic evaluated fresh on every clock edge, an up/down counter does not need to be reset or reinitialized to reverse direction — changing UP simply changes which toggle condition (carry vs. borrow) governs the very next clock edge, and the counter continues from wherever it currently is, now stepping the opposite way. For example, a counter sitting at 5 with UP=1 will go to 6 on the next clock; if UP is instead set to 0 before that same clock edge, the counter goes to 4 instead — same current state, opposite next state, purely because the direction input changed.
This flexibility, however, comes with a timing requirement: the UP/DOWN control line is itself an input to synchronous logic, and like any such input it must satisfy setup and hold time relative to the clock edge that samples it (Topic 7.5, Setup/Hold). Changing direction in the middle of a clock's active-edge window, rather than safely before it with adequate setup time, risks the same kind of unpredictable or metastable behavior any synchronous input violation can cause.
Practical application, real-world use, and common mistake
Up/down counters directly model any physical quantity that can move in either direction: an elevator's floor counter increments while ascending and decrements while descending; a motor or shaft encoder's position counter increments for forward rotation and decrements for reverse rotation, giving downstream logic a running position value with no separate arithmetic needed; a digital volume or brightness control increments on one button and decrements on another, using the exact same counter hardware for both.
The common mistake is changing the UP/DOWN control asynchronously, exactly at or near the active clock edge, without treating it as a properly synchronized control signal. Because the direction line feeds directly into the same combinational excitation logic that determines every bit's next value, an unsynchronized, glitchy, or metastable direction change right at the sampling instant can produce an unpredictable next state — not simply 'the wrong direction for one cycle,' but potentially a corrupted count value. Direction changes should be synchronized to the clock domain exactly like any other control input to a synchronous circuit.
Up/down counter control and excitation logic
Exact control polarity (which level means 'up') is implementation-defined; this matches the spec's stated typical convention. Some commercial parts use two separate clock inputs (count-up clock, count-down clock) instead of one shared clock plus a direction line — check the specific IC.
Direction control (typical convention -- confirm against the datasheet in use):
UP = 1 -> count up
UP = 0 -> count down
Excitation (T flip-flops), bit k (0-indexed):
T0 = 1
Tk = (UP . [Q0 . Q1 . ... . Q(k-1)]) -- up-mode carry condition
+ (NOT UP . [NOT Q0 . NOT Q1 . ... . NOT Q(k-1)]) -- down-mode borrow condition
('.' = AND, '+' = OR)Code Examples
The counter counts up through clocks 2 and 3 while UP=1. At clock 4, UP has already been switched to 0 before the active edge, so from clock 5 onward the same excitation logic now selects the down-mode (borrow) condition instead of the up-mode (carry) condition, and the counter proceeds downward from wherever it was — no reset or reinitialization needed to change direction. Expected result: Sequence: 0, 1, 2, (direction reversed), 1, 0, ...
Changing UP does not reset the counter — it simply changes which toggle condition (carry vs. borrow) governs the very next clock edge from the counter's current state.
Clock# UP Q2 Q1 Q0 Decimal Action
1 1 0 0 0 0 (start, counting up)
2 1 0 0 1 1 up: 0 -> 1
3 1 0 1 0 2 up: 1 -> 2
4 0 0 1 0 2 (UP switched to 0 before this edge; state unchanged yet)
5 0 0 0 1 1 down: 2 -> 1
6 0 0 0 0 0 down: 1 -> 0Up/down counter: direction mux feeding shared excitation logic
Each stage's toggle input is selected between an up-mode and down-mode condition based on the shared UP control line.
UP
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+-----------+-----------+
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[up-mode carry logic] [down-mode borrow logic]
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+-----------+-----------+
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(2:1 select by UP)
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T_k input --> Flip-flop kImportant Rules
A single UP/DOWN control line (or, on some ICs, separate up-clock and down-clock inputs) selects which of the two toggle conditions — carry (up) or borrow (down) — governs each stage on the next clock edge.
Reversing direction does not require resetting the counter — it simply changes the excitation logic's active branch, and counting continues from the current state in the new direction.
The direction control line must be synchronized to the clock like any other synchronous input; changing it too close to the active edge risks setup/hold violations and an unpredictable next state.
Position and quantity tracking in both directions
Up/down counters are the standard building block for anything that tracks a bidirectional physical or user-driven quantity in hardware: elevator floor position (up while ascending, down while descending), motor shaft-encoder position tracking (forward vs. reverse rotation), and digital volume, brightness, or setting controls where one button increments and another decrements the same underlying count.
Toggling the UP/DOWN control signal asynchronously, right at or near the clock's active edge, without treating it as a synchronized input.
Change the direction control line safely before the clock's setup-time window (synchronize it to the clock domain like any other control input), so the excitation logic sampling it at the active edge sees a clean, stable value rather than a signal that might still be transitioning.
The direction input feeds directly into the same combinational logic that determines every bit's next state; violating its setup/hold timing can produce not just 'one cycle in the wrong direction' but a genuinely corrupted, unpredictable next count value, exactly the kind of hazard covered generally in the setup/hold and metastability topics.
[conceptual] How does an up/down counter's internal excitation logic differ from a plain up counter's? A. It uses a completely separate, unrelated flip-flop design B. Each stage's toggle logic is a mux selecting between the up counter's carry-toggle condition and the down counter's borrow-toggle condition, chosen by a shared direction-control input C. It has no excitation logic at all — direction is set by physically rewiring the circuit D. It only works with asynchronous ripple-style clocking, never synchronous
B. Each stage's toggle logic is a mux selecting between the up counter's carry-toggle condition and the down counter's borrow-toggle condition, chosen by a shared direction-control input — An up/down counter is built by combining both the up counter's and down counter's excitation equations at each stage, with a direction-control input (UP) selecting which one is active for the upcoming clock edge — it is not a separate design from scratch, but a direct combination of the two single-direction counters' logic.
[interview] Why must the UP/DOWN direction input to a synchronous up/down counter be synchronized to the clock, rather than changed freely at any moment? A. Because the direction input directly controls the clock frequency B. Because the direction line feeds the same combinational excitation logic sampled by the flip-flops on the active clock edge, so a change too close to that edge can violate setup/hold timing and produce an unpredictable, potentially corrupted next state C. Because up/down counters do not actually support changing direction while running D. Because the direction input must always equal the clock signal itself
B. Because the direction line feeds the same combinational excitation logic sampled by the flip-flops on the active clock edge, so a change too close to that edge can violate setup/hold timing and produce an unpredictable, potentially corrupted next state — Like any input to synchronous logic, the direction control line must be stable through the flip-flops' setup and hold window around the active clock edge. Since it directly selects which excitation branch (carry vs. borrow) is used to compute the next state, an unsynchronized or glitchy change near that edge risks a genuinely corrupted count, not just a harmless one-cycle direction blip.
A rotary shaft encoder produces a pulse on CLK for every detent it turns, and a separate DIR signal that is high when turning clockwise and low when turning counter-clockwise. Describe how you would wire a synchronous up/down counter to track the shaft's absolute position, and note the one timing precaution you must take with DIR.
Wire the encoder's CLK pulses to the counter's clock input and the encoder's DIR signal to the counter's UP control input (DIR=clockwise mapped to UP=1, DIR=counter-clockwise mapped to UP=0). The counter's current value Q then continuously reflects the shaft's absolute position relative to its starting point, incrementing per clockwise detent and decrementing per counter-clockwise detent. The precaution: because DIR comes from external mechanical hardware, it should be synchronized (e.g., passed through its own synchronizer flip-flops) and stable well before each CLK edge's setup-time window, so a direction change occurring near a clock edge doesn't risk corrupting that edge's next-state computation.
Map DIR directly to the counter's UP input, and remember DIR must be stable and synchronized before each CLK edge, not changing right at the edge.