12.4 Fan-Out: How Many Loads an Output Can Drive

Compute fan-out from current specifications, and explain why fan-out is an electrical loading limit rather than simply 'how many wires leave a pin.'

Fan-out is the number of standard input loads a single gate output can reliably drive while still guaranteeing valid logic levels at every one of those loads. It is easy to misread a schematic and think fan-out is just 'count the arrows leaving this pin,' but the spec's own framing is the important correction: fan-out is fundamentally an electrical loading concept — governed by how much current (or, in CMOS, how much capacitance) the driving output can supply compared to how much every downstream input demands — not a count derived purely from the drawing.

Core concept: current-limited fan-out (TTL)

For a current-sinking/sourcing family like TTL, fan-out is set by comparing the driver's guaranteed output drive current against each load's guaranteed input current demand, separately for both logic states, and taking the more restrictive of the two: FO = min( IOL(max)/IIL , IOH(max)/IIH ). A standard TTL output can sink up to 16 mA (IOL max) while a standard TTL input sinks (i.e., demands) 1.6 mA when driven LOW (IIL); dividing gives 16/1.6 = 10 loads from the LOW-state limit. On the HIGH side, a standard output can source up to 400 µA (IOH max) while a standard input draws 40 µA when driven HIGH (IIH); dividing gives 400/40 = 10 loads. Both limits agree at 10 — the textbook 'standard TTL fan-out is 10' number, and it is not a coincidence that both numbers match; the family's specs were defined together specifically so the same '10 standard loads' figure applies in both directions.

If a design mixes subfamilies (e.g., a 74LS driving several 74S inputs), the current numbers differ per subfamily, and the correct fan-out calculation must use the *specific* IIL/IIH of the actual loads being driven, not the generic 'standard load' figures — a mixed-family fan-out calculation is a very common exam and interview question.

Core concept: capacitance-limited fan-out (CMOS)

CMOS inputs draw almost no DC current (they're high-impedance MOSFET gates), so the current-based fan-out formula above is nearly meaningless for a CMOS receiver — by that measure CMOS fan-out looks enormous. But CMOS inputs still present real *capacitance* that the driving gate's output must charge and discharge on every transition, and every additional load adds to the total capacitance the driver sees. More load capacitance means a slower RC-driven transition (longer propagation delay), so in CMOS-to-CMOS systems, fan-out isn't bounded by a fixed 'maximum number of loads' the way TTL is — it's bounded by 'how much delay can this timing path tolerate,' which is a design-specific, speed-dependent limit rather than a fixed DC number.

This is why datasheets for CMOS logic families often specify fan-out indirectly, through output drive strength (current at a given VOL/VOH) combined with a maximum recommended load capacitance for a target speed grade, rather than a single flat 'fan-out = N' figure the way older TTL datasheets did.

Fan-out formula (current-limited families)

FO = min( IOL(max) / IIL , IOH(max) / IIH )

Standard TTL example:
  IOL(max) = 16 mA,   IIL = 1.6 mA  → 16/1.6  = 10
  IOH(max) = 400 µA,  IIH = 40 µA   → 400/40  = 10
  FO = min(10, 10) = 10 standard loads

Code Examples

Because 74LS inputs draw much less current than standard-load TTL inputs, a standard TTL output can drive far more than 10 of them — but the two directions (LOW-state sinking vs HIGH-state sourcing) don't scale identically, so the HIGH-side limit of 20 is what actually caps this driver, not the LOW-side limit of 40. Always take the *minimum* of the two calculations, never just one.

Fan-out is the minimum of the LOW-state and HIGH-state load calculations — never just one direction.

Driver: standard 74xx TTL output   IOL(max)=16mA,  IOH(max)=400µA
Loads:  74LS inputs                IIL=0.4mA,      IIH=20µA

FO(LOW side)  = 16mA  / 0.4mA = 40
FO(HIGH side) = 400µA / 20µA  = 20

FO = min(40, 20) = 20

Important Rules

Fan-out = min(IOL(max)/IIL, IOH(max)/IIH) for current-limited (bipolar/TTL) families — always compute both directions and take the smaller.

CMOS fan-out is primarily capacitance-limited, not current-limited — more loads mean slower edges, not exceeded current ratings.

Mixed-family fan-out must use the actual IIL/IIH of the specific receiving parts, not generic 'standard load' numbers.

Fan-out is an electrical current/capacitance loading limit, not simply a count of wires or gates drawn on a schematic.

Bus drivers and buffer ICs

When a signal must fan out to more loads than its native driver can support — for example, a single clock or control signal that must reach dozens of chips on a backplane — engineers insert dedicated buffer/driver ICs (high-current clock buffers, bus transceivers) specifically designed with much higher IOL/IOH ratings than a typical logic gate, restoring margin rather than simply hoping the original driver can cope.

Counting the number of gate inputs connected to an output on the schematic and calling that 'the fan-out.'

Look up (or calculate) the driver's guaranteed output current/capacitance drive and each load's actual current/capacitance demand, and compute the electrical limit.

Two schematics that look identical (one output fanning out to five gates) can have completely different real fan-out margins depending on which specific logic subfamilies are involved — the wire count on the page carries no electrical information by itself.

Why can a CMOS output typically 'drive' vastly more CMOS input loads than a TTL fan-out number of 10, in terms of raw count? A. CMOS outputs are simply built with more powerful transistors B. CMOS inputs draw almost no DC current, so the current-based limit that caps TTL fan-out barely applies; the real CMOS constraint is capacitive loading and its effect on switching speed, not a fixed load count C. CMOS logic doesn't obey the laws of electrical loading D. CMOS fan-out is always exactly double TTL fan-out by specification

B. CMOS inputs draw almost no DC current, so the current-based limit that caps TTL fan-out barely applies; the real CMOS constraint is capacitive loading and its effect on switching speed, not a fixed load count — TTL fan-out is capped by DC input current draw (IIL/IIH), which CMOS inputs barely have. CMOS instead accumulates load *capacitance*, which slows edges rather than exceeding a current rating — so 'CMOS fan-out' is really a speed budget, not a fixed maximum count, which is why it isn't meaningfully compared to TTL's number-of-loads figure.

A designer computes fan-out using only the HIGH-state (IOH/IIH) numbers and ignores the LOW-state (IOL/IIL) numbers. What is the risk? A. None — HIGH-state numbers always dominate in practice B. If the LOW-state ratio is smaller than the HIGH-state ratio, the true fan-out limit (the minimum of the two) is lower than what was calculated, risking a driver that can't guarantee valid VOL under worst-case loading C. This only matters for CMOS, never for TTL D. Fan-out only needs to be checked in one direction by definition

B. If the LOW-state ratio is smaller than the HIGH-state ratio, the true fan-out limit (the minimum of the two) is lower than what was calculated, risking a driver that can't guarantee valid VOL under worst-case loading — Fan-out must be computed as the minimum of the two independent limits (LOW-state sinking and HIGH-state sourcing) because a real driver must satisfy both simultaneously across all loads. Checking only one direction can produce an overly optimistic fan-out number that fails in the other logic state under worst-case conditions.

A 74LS gate output (IOL(max)=8mA, IOH(max)=400µA) must drive six standard 74xx TTL inputs (IIL=1.6mA, IIH=40µA). Is this within the driver's fan-out capability? Show the calculation for both directions.

LOW side: 8mA / 1.6mA = 5. HIGH side: 400µA / 40µA = 10. FO = min(5, 10) = 5. The driver can reliably support only 5 standard loads, but 6 are connected — this exceeds the LOW-state sink capability, so the design is out of spec and would likely fail to reach a valid VOL under worst-case conditions; either reduce the load count or use a driver with higher IOL(max).

Compute FO for the LOW side and HIGH side separately, take the minimum, and compare it against 6.