10.3 Synchronous Counter
Explain how a synchronous counter uses a shared clock plus per-stage next-state logic to avoid ripple delay, and derive the toggle (excitation) equations for a synchronous binary up-counter.
A synchronous counter clocks every flip-flop from the same shared clock signal, exactly like a register, and instead computes each flip-flop's next value with dedicated combinational next-state (excitation) logic that looks at the entire current state — this eliminates the ripple delay of an asynchronous counter at the cost of extra gates. It exists because many applications need a counter that can run at much higher clock frequencies, or whose outputs must all change at the same instant (for glitch-free decoding), and synchronous design is the standard technique for achieving both.
Core concept: one shared clock, per-stage excitation logic
In a synchronous counter, every flip-flop's clock input is tied to the same external clock line, so every stage that needs to change does change at exactly the same instant, on the same edge — there is no rippling, because no stage's clock depends on another stage's output. What replaces the ripple chain is combinational logic in front of each flip-flop's control input (its T input for a toggle-based design, or D/J-K inputs for other designs) that computes, from the entire present state, whether that particular flip-flop should toggle on the upcoming clock edge.
For a synchronous binary up-counter built from T flip-flops, the excitation equations follow the carry pattern of binary addition: T0 = 1 (the LSB always toggles, every single clock); T1 = Q0 (the next bit toggles only when the LSB is currently 1, i.e., only when incrementing it would produce a carry); T2 = Q0 AND Q1 (the third bit toggles only when both lower bits are 1); and in general, Tk = AND of all bits below position k. This is exactly the carry-propagation logic of binary addition, just implemented as combinational gates feeding flip-flop toggle inputs instead of an adder circuit.
• Every flip-flop shares one clock — updates happen simultaneously, with no per-stage rippling. • Each stage needs its own next-state (excitation) logic computed from the whole current state, not just the previous stage's output. • Binary up-counter toggle pattern: Tk = AND of all lower bits (Q0 through Q(k-1)) — mirrors binary-addition carry propagation.
Step-by-step: why not every bit toggles on every clock
This is exactly the spec's tricky point for synchronous counters: sharing a clock means every flip-flop is clocked on every edge, but it does not mean every flip-flop's stored value changes on every edge — whether a given stage actually toggles depends entirely on that stage's own excitation logic evaluating true for the current state, not merely on the presence of a clock edge. In a synchronous binary up-counter, Q0 toggles on literally every clock edge (T0 = 1, unconditionally), but Q1 only toggles on the clock edges where Q0 currently equals 1 (T1 = Q0), and Q2 only toggles when both Q0 and Q1 are currently 1 (T2 = Q0 AND Q1).
Tracing a 3-bit synchronous up-counter through its 8-state cycle shows this directly: Q0 flips every single row; Q1 flips only every other row (whenever the previous row had Q0=1); Q2 flips only once every four rows (whenever the previous row had Q0=Q1=1) — the exact same overall count sequence as the ripple counter from Topic 10.2, but produced by parallel, simultaneously-clocked excitation logic rather than a chain of sequentially-triggered stages.
Practical application, real-world use, and common mistake
Because a synchronous counter's maximum speed is limited only by one flip-flop's clock-to-Q delay plus the propagation delay through its (typically shallow) excitation logic — not by a delay that accumulates with every additional stage — synchronous counters are the standard choice anywhere high-speed counting is required: CPU internal timers, high-frequency event counters, and any counter whose decoded outputs feed time-critical downstream logic, where the ripple counter's transient glitch states (Topic 10.2) would be unacceptable.
The common mistake, echoing the spec's tricky point directly, is assuming 'synchronous' is synonymous with 'every bit changes every clock.' In reality, synchronicity refers purely to the clocking scheme (one shared clock edge for every stage) — whether a particular bit's value actually changes on a given edge is governed entirely by that bit's own excitation logic and the current state, exactly as in a ripple counter's underlying count sequence, just computed differently.
Synchronous up-counter excitation equations
'.' denotes logical AND in these excitation equations. This T-input pattern is the synchronous counter's direct analogue of a ripple-carry adder's carry chain.
n-bit synchronous binary up-counter, T flip-flops, shared CLK:
T0 = 1 (LSB always toggles)
T1 = Q0
T2 = Q0 . Q1
T3 = Q0 . Q1 . Q2
...
Tk = Q0 . Q1 . ... . Q(k-1) (AND of all lower bits)
All flip-flops share one CLK; T_k feeds flip-flop k's toggle input;
on the shared active edge, flip-flop k toggles iff T_k currently = 1.Code Examples
T0 is 1 in every row, so Q0 toggles every single clock. T1 is only 1 in rows where Q0 was already 1, so Q1 toggles roughly every other clock. T2 is only 1 in rows where both Q0 and Q1 were 1, so Q2 toggles only once every four clocks — yet every single row's transition happens on the same shared clock edge, with no rippling between stages. Expected result: Sequence produced: 000, 001, 010, 011, 100, 101, 110, 111, 000, ... — identical count sequence to the ripple counter, produced without any ripple delay.
Same shared clock edge for every row, but T0/T1/T2 are not all 1 at once — each stage's actual toggling depends on its own excitation logic, not merely on the clock.
Before Q2 Q1 Q0 | T2=Q0.Q1 T1=Q0 T0=1 | After Q2 Q1 Q0
0 0 0 | 0 0 1 | 0 0 1
0 0 1 | 0 1 1 | 0 1 0
0 1 0 | 0 0 1 | 0 1 1
0 1 1 | 1 1 1 | 1 0 0
1 0 0 | 0 0 1 | 1 0 1
1 0 1 | 0 1 1 | 1 1 0
1 1 0 | 0 0 1 | 1 1 1
1 1 1 | 1 1 1 | 0 0 0Synchronous counter: shared clock, parallel excitation logic
Every stage is clocked simultaneously; only the excitation (T-input) logic differs per stage, avoiding any ripple delay.
Q0 Q1 Q2
| | |
T0=1 | T1=Q0 | T2=Q0.Q1|
\ v \ v \ v
[FF0]<-CLK [FF1]<-CLK [FF2]<-CLK
(all three FF clock inputs tied to the SAME CLK line)Important Rules
Every flip-flop in a synchronous counter shares one common clock signal — all stages that need to change do so on the exact same edge.
Each stage needs its own combinational excitation logic evaluated from the entire current state, not just the neighboring bit — this is the extra hardware cost synchronous design pays for eliminating ripple delay.
A synchronous counter's maximum speed is bounded by one flip-flop delay plus the excitation logic's propagation delay, not by a per-stage-accumulating chain, so it scales to much higher frequencies than a ripple counter of the same width.
High-speed counters and timers
CPU internal cycle counters, hardware performance-monitoring counters, PLL feedback dividers, and any high-frequency event counter that must decode its output reliably at speed all use synchronous counter design, because their required clock frequencies and glitch-free decoding needs make a ripple counter's accumulating settling delay and transient glitch states unacceptable.
Assuming that because a synchronous counter uses one shared clock, every bit must change value on every single clock edge.
A shared clock only means every flip-flop is evaluated at the same instant — whether a particular bit actually toggles on that edge depends entirely on its own excitation logic (e.g., T1 = Q0 only toggles Q1 when Q0 is currently 1), exactly mirroring the natural carry-toggle pattern of binary counting.
This is precisely the spec's tricky point: synchronicity is about clock timing (all stages sampled on one shared edge), not about whether every stage's stored value changes on that edge — that is governed by the next-state/excitation logic, and behaves identically to an equivalent ripple counter's underlying count sequence, just without the rippling delay.
[tricky-problem] All flip-flops in a synchronous counter receive the same clock signal. Does this mean every flip-flop's output changes on every single clock edge? A. Yes, by definition of 'synchronous' B. No — sharing a clock only means every flip-flop is evaluated at the same instant; whether a given stage's value actually changes depends on that stage's own excitation (next-state) logic and the current state, not merely on the clock edge occurring C. No, because synchronous counters only update one bit per clock edge total D. Yes, but only for down-counters, not up-counters
B. No — sharing a clock only means every flip-flop is evaluated at the same instant; whether a given stage's value actually changes depends on that stage's own excitation (next-state) logic and the current state, not merely on the clock edge occurring — This is the spec's explicit tricky point: 'synchronous' describes the clocking scheme, not the toggling behavior of every bit. In a synchronous up-counter, only the LSB toggles unconditionally every clock; every higher bit toggles only when its excitation logic (an AND of all lower bits) is currently true, exactly like carry propagation in binary addition.
[interview] What is the main hardware cost a synchronous counter pays in exchange for eliminating ripple delay? A. It requires twice as many flip-flops as a ripple counter of the same width B. It requires per-stage combinational excitation (next-state) logic derived from the entire current state, rather than simply chaining one stage's output into the next stage's clock C. It cannot count higher than 15 D. It requires an external oscillator that a ripple counter does not need
B. It requires per-stage combinational excitation (next-state) logic derived from the entire current state, rather than simply chaining one stage's output into the next stage's clock — A ripple counter needs almost no extra logic beyond the toggle flip-flops themselves, because each stage's own output directly clocks the next. A synchronous counter instead needs dedicated AND-gate (or equivalent) excitation logic per stage, computed from the whole current state, so that every stage can be driven from one shared clock and still toggle correctly — more gates, but no accumulating ripple delay.
Derive the excitation equation T3 for a 4-bit synchronous binary up-counter (bits Q3 Q2 Q1 Q0, T flip-flops), following the same carry-propagation pattern used for T0, T1, and T2.
T3 = Q0 . Q1 . Q2 — the fourth bit (Q3) toggles synchronously only on the clock edge where all three lower bits (Q0, Q1, and Q2) are currently 1, exactly mirroring the carry-out condition of adding 1 to a binary number whose three lowest bits are all set.
Follow the pattern Tk = AND of all bits strictly below position k.