8.1 SR Flip-Flop: Set-Reset Storage and Its Forbidden State

Build and analyze the truth table of both NOR-based and NAND-based SR latches, and correctly identify each implementation's forbidden input combination.

The SR (Set-Reset) flip-flop is the conceptual ancestor of every other flip-flop in this module — historically and pedagogically, it is the first storage element most students build, typically from just two cross-coupled NOR or NAND gates. It directly demonstrates how feedback creates memory (the exact structural idea from Topic 7.1), but it also comes with a well-known flaw — a forbidden input combination — that motivates the JK flip-flop covered next in Topic 8.2.

Core Concept: Set, Reset, and Two Different Gate Implementations

An SR flip-flop (or, in its unclocked form, an SR latch) has two inputs: S (Set) and R (Reset). Asserting S drives the stored output Q to 1 (sets it); asserting R drives Q to 0 (resets it); and with neither asserted, the circuit holds its previous value via feedback, exactly as described structurally in Topic 7.1. This much is universal across every SR implementation — but the crucial detail this module flags explicitly is that the exact meaning of "asserted" and the resulting forbidden combination depend entirely on which gate type the latch is built from.

A NOR-based SR latch uses active-high inputs: S=1 sets, R=1 resets, and the invalid (forbidden) combination is S=1 AND R=1 simultaneously — in that case both outputs Q and Q' are forced to 0 together, which violates the basic requirement that Q and Q' always be complementary, and produces an unpredictable, race-prone result the instant both inputs are released. A NAND-based SR latch (often written S'R' to emphasize its active-low inputs) instead sets on S'=0, resets on R'=0, holds when both are 1, and its forbidden combination is exactly the opposite polarity: S'=0 AND R'=0 simultaneously.

• S = Set input: asserting it forces Q toward 1. • R = Reset input: asserting it forces Q toward 0. • The specific forbidden combination depends on the gate technology (NOR-based vs. NAND-based) — never assume one universal truth table.

Step-by-Step: Behavior in Each Implementation

For the NOR-based (active-high) SR latch: S=0,R=0 holds the previous state; S=1,R=0 sets Q=1; S=0,R=1 resets Q=0; and S=1,R=1 is forbidden. For the NAND-based (active-low) S'R' latch: S'=1,R'=1 holds; S'=0,R'=1 sets Q=1; S'=1,R'=0 resets Q=0; and S'=0,R'=0 is forbidden. Notice the two tables are structurally mirror images of each other with respect to which input level does what — which is exactly why blindly memorizing a single SR truth table without first checking whether the specific circuit is NOR-based or NAND-based is a guaranteed way to get the forbidden-state condition backward.

Tricky Concept: Why the Forbidden State Is a Real Problem

The forbidden combination is not merely "undefined" in some abstract theoretical sense — it produces a real physical hazard. While both inputs are simultaneously asserted, Q and Q' are forced to the same value (both 0 in the NOR case), breaking the fundamental assumption that they are always complements of each other. Worse, if both inputs are then released back to their inactive level at exactly the same instant, the two cross-coupled gates race to determine the final state, and which one "wins" depends on minute manufacturing differences in gate delay — the outcome becomes genuinely unpredictable. This exact race-condition weakness is precisely what motivates the JK flip-flop in the next topic, which eliminates the forbidden combination entirely by redefining it as a useful toggle operation instead.

SR flip-flop / latch truth tables (both implementations)

S = Set, R = Reset (module's own notation). The forbidden row's exact output value (both 0 vs. both 1) also flips between the two implementations — another detail that trips up rote memorization.

NOR-based SR latch (active-HIGH inputs):
  S | R | Q(next)
  --|---|--------
  0 | 0 | hold (previous Q)
  1 | 0 | 1 (Set)
  0 | 1 | 0 (Reset)
  1 | 1 | FORBIDDEN (Q = Q' = 0)

NAND-based S'R' latch (active-LOW inputs):
  S'| R'| Q(next)
  --|---|--------
  1 | 1 | hold (previous Q)
  0 | 1 | 1 (Set)
  1 | 0 | 0 (Reset)
  0 | 0 | FORBIDDEN (Q = Q' = 1)

Code Examples

Steps 1-4 are all well-defined: Reset drives Q to 0, holding preserves it, Set drives Q to 1, and holding again preserves the 1. Step 5 asserts both S and R simultaneously on this NOR-based (active-high) latch — the forbidden combination — driving both Q and Q' to 0 together, violating their complementary relationship and creating a race hazard if both inputs are released at once afterward. Expected result: Q sequence: 0, 0(hold), 1, 1(hold), FORBIDDEN

S=1,R=1 on a NOR-based SR latch is the forbidden state — never assume this is universal without checking the gate type.

step  S  R   Q(next)
1     0  1   0        (Reset)
2     0  0   0        (Hold — stays 0)
3     1  0   1        (Set)
4     0  0   1        (Hold — stays 1)
5     1  1   FORBIDDEN

Cross-coupled NOR gate SR latch

Each NOR gate's output feeds back as an input to the other gate — this cross-coupling is exactly the feedback loop that Topic 7.1 identifies as the structural signature of sequential (memory) behavior.

_____
  S -->|     |
       | NOR |---+---> Q
   +-->|_____|   |
   |              |
   |    _____     |
   +---|     |    |
       | NOR |----+---> Q'
  R -->|_____|

  Feedback: Q feeds the R-side NOR, Q' feeds the S-side NOR

Important Rules

S (Set) forces Q toward 1; R (Reset) forces Q toward 0; neither asserted holds the previous state.

The forbidden combination's polarity depends on the implementation: NOR-based is S=1,R=1; NAND-based (S'R') is S'=0,R'=0.

Never assume a single universal SR truth table — always confirm whether the specific circuit is NOR-based (active-high) or NAND-based (active-low) first.

The forbidden state breaks the Q/Q' complementary relationship and creates an unpredictable race if both inputs release simultaneously.

SR latches as the basic memory building block

Even though the SR latch's forbidden state makes it unsuitable as a general-purpose flip-flop on its own, it remains foundational: it is the simplest possible bistable memory cell, it appears as a component inside more sophisticated latches and debounce circuits (for cleaning up the multiple rapid transitions a mechanical switch produces when pressed), and understanding its cross-coupled feedback structure directly is what makes the master-slave flip-flop architecture in Topic 8.5 intuitive rather than mysterious.

Circuit Symbol

IEEE block symbol for the SR flip-flop: S and R data inputs on the left, CLK with its clock-edge indicator, Q and Q' complementary outputs on the right.

Memorizing "S=1, R=1 is always the forbidden combination" and applying it to every SR-type latch encountered.

Always identify the gate technology first — for a NAND-based S'R' latch (active-low inputs), the forbidden combination is S'=0, R'=0, not S=1,R=1.

This is the module's own explicit tricky problem: do not memorize an SR truth table without checking whether the implementation is NOR-based or NAND-based, since the active levels — and therefore the forbidden row — are opposite between the two.

[tricky-problem] A student memorizes that S=1, R=1 is always the invalid/forbidden combination for an SR flip-flop, and applies this rule to a circuit built from NAND gates with active-low inputs. Is this correct? A. Yes — S=1, R=1 is universally forbidden for every SR implementation B. No — for a NAND-based S'R' latch (active-low inputs), the forbidden combination is S'=0, R'=0, the opposite polarity; the implementation must be checked before applying any SR truth table C. No — NAND-based SR latches have no forbidden state at all D. Yes, but only if the clock is also high

B. No — for a NAND-based S'R' latch (active-low inputs), the forbidden combination is S'=0, R'=0, the opposite polarity; the implementation must be checked before applying any SR truth table — This is the module's exact tricky problem: do not memorize an SR truth table without checking whether the implementation is NOR-based or NAND-based. NOR-based (active-high) latches forbid S=1,R=1; NAND-based S'R' (active-low) latches forbid S'=0,R'=0 — applying the NOR rule to a NAND-based circuit gets the forbidden condition exactly backward.

Why is the SR flip-flop's forbidden state considered a genuine hazard rather than just a theoretical inconvenience? A. It draws excessive power compared to other input combinations B. It forces Q and Q' to the same value (breaking their required complementary relationship), and releasing both inputs simultaneously afterward creates an unpredictable race between the two cross-coupled gates C. It permanently damages the gates D. It only matters in software simulation, never in real hardware

B. It forces Q and Q' to the same value (breaking their required complementary relationship), and releasing both inputs simultaneously afterward creates an unpredictable race between the two cross-coupled gates — In the forbidden state, both Q and Q' are driven to the same logic value, violating the basic assumption that they are complements. If both S and R are then released at the same instant, which gate 'wins' the race back to a valid state depends on microscopic manufacturing differences in gate delay — a genuinely unpredictable real physical outcome, not just an abstract 'undefined' entry in a truth table.

You are handed a physical two-gate latch and told only that it is SR-type, with no schematic. By experimentally driving both inputs to 0 simultaneously, you observe that Q immediately becomes 1. Is this a NOR-based or NAND-based SR latch, and what input combination would you now expect to be forbidden?

Driving both inputs to 0 and getting Q=1 (rather than a hold or a forbidden result) identifies this as a NAND-based S'R' latch, where 0 is the active (asserting) level and both inputs asserted (0,0) is actually the FORBIDDEN state for that implementation — meaning this particular observation must have actually been a single-input assertion, not both simultaneously, or the latch is behaving as expected only if just one input was truly 0. The key diagnostic point: on a NAND-based S'R' latch, holding requires BOTH inputs at 1, and the forbidden row is S'=0,R'=0 — the opposite polarity from the NOR-based version.

Recall which implementation treats which input level as the "inactive/hold" level, and cross-reference against the observed set/reset direction.