8.2 JK Flip-Flop: Solving the SR Forbidden State

State the JK flip-flop's truth table and characteristic equation, and explain how it eliminates the SR flip-flop's forbidden combination by redefining it as toggle.

The JK flip-flop takes the SR flip-flop from Topic 8.1 and fixes its one glaring weakness: instead of leaving the S=1,R=1 combination forbidden, the JK flip-flop redefines that same input combination to mean toggle — flip to the opposite of the current state. This single design change removes every invalid input combination from the device entirely, at the cost of introducing a new, more subtle timing hazard (the race-around problem) that is fully resolved by the master-slave structure in Topic 8.5.

Core Concept: Every Input Combination Is Now Valid

A JK flip-flop has two inputs, J and K, that behave exactly like S and R for three of the four possible combinations: J=0,K=0 holds the current state; J=0,K=1 resets Q to 0; J=1,K=0 sets Q to 1. The change is in the fourth row — where SR would have been forbidden, JK instead defines J=1,K=1 as toggle: Q flips to the opposite of whatever it currently is. Because toggling still produces a single, well-defined next state (not an ambiguous or invalid one), there is no longer any input combination that breaks the circuit's basic correctness.

This directly matches the module's own framing: JK removes the invalid SR combination in the classic implementation. The name itself is simply a historical convention (J and K do not stand for anything related to Set/Reset — they are commonly attributed to engineer Jack Kilby, though the etymology is debated); functionally, think of J as "Set-like" and K as "Reset-like", with the crucial addition of a well-defined toggle behavior when both are asserted together.

• J=0, K=0: Hold (no change). • J=0, K=1: Reset (Q → 0). • J=1, K=0: Set (Q → 1). • J=1, K=1: Toggle (Q → NOT Q) — this is the row that was forbidden on a plain SR flip-flop.

Step-by-Step: The Characteristic Equation

The JK flip-flop's next-state behavior can be captured in a single Boolean characteristic equation: Q(next) = J·Q' + K'·Q. Checking this against the truth table confirms it matches every row: when J=0,K=0, the equation reduces to Q(next) = 0 + 1·Q = Q (hold); when J=0,K=1, it reduces to Q(next) = 0 + 0 = 0 (reset); when J=1,K=0, it reduces to Q(next) = Q' + Q = 1 (set, since Q' + Q is always 1 regardless of Q's value); and when J=1,K=1, it reduces to Q(next) = Q' + 0 = Q' (toggle — the next state is exactly the complement of the current state, which is precisely the toggle behavior).

This characteristic equation is the tool used throughout Topic 8.6 (Flip-Flop Conversion): because it expresses Q(next) purely in terms of J, K, and the current Q, it can be algebraically manipulated to design conversion logic between JK and any other flip-flop type.

Tricky Concept: The Race-Around Problem

Eliminating the forbidden state does not eliminate every hazard — it trades the SR flip-flop's static forbidden-combination problem for a new dynamic timing problem specific to level-triggered JK implementations. If a JK flip-flop is built as a simple level-sensitive device (transparent for the entire duration the clock is high, similar to a latch) and J=K=1 is held steady for that entire high period, the output can toggle repeatedly within a single clock pulse — because each toggle changes Q, which feeds back into the same gates that are still "listening" while the clock remains high, causing it to toggle again, and again, an unpredictable number of times before the clock finally goes low. This is called the race-around problem, and it is precisely what motivates the master-slave JK flip-flop structure in Topic 8.5, which breaks the direct feedback path during the transparent window so exactly one toggle occurs per clock cycle, no matter how long the clock pulse stays high.

JK flip-flop characteristic equation and excitation table

X = don't-care — either 0 or 1 works for that input in that transition, giving design flexibility used heavily in Topic 8.6.

Characteristic equation: Q(next) = J*Q' + K'*Q

J | K | Action
--|---|-------
0 | 0 | Hold
0 | 1 | Reset
1 | 0 | Set
1 | 1 | Toggle

Excitation table (given Q -> Q(next), required J,K):
Q | Q+ | J | K
--|----|---|---
0 | 0  | 0 | X
0 | 1  | 1 | X
1 | 0  | X | 1
1 | 1  | X | 0

Code Examples

Apply the truth table row by row, using each step's resulting Q as the next step's starting Q. Edge 1 sets Q to 1. Edge 2 holds it. Edges 3 and 4 both have J=K=1, so Q simply flips each time (1→0, then 0→1) — this is the toggle behavior that replaced the SR flip-flop's forbidden state. Edge 5 resets Q back to 0. Expected result: Q sequence: 1, 1, 0, 1, 0

J=1,K=1 always flips Q to its complement — Q(next) = Q', consistent with the characteristic equation Q(next) = J·Q' + K'·Q reducing to Q' when J=K=1.

edge  J  K   Q(before)  Q(next)   Action
1     1  0   0          1         Set
2     0  0   1          1         Hold
3     1  1   1          0         Toggle
4     1  1   0          1         Toggle
5     0  1   1          0         Reset

JK flip-flop symbol

J behaves like Set, K behaves like Reset, and the clock triangle marks edge-triggered sampling — the J=K=1 combination toggles Q rather than being forbidden.

______
  J -->|      |
       |  JK  |--> Q
  K -->|      |--> Q'
  clk->|>_____|

Important Rules

J=0,K=0 holds; J=0,K=1 resets; J=1,K=0 sets; J=1,K=1 toggles — every combination is valid, unlike plain SR.

Characteristic equation: Q(next) = J·Q' + K'·Q.

A naive level-triggered JK implementation is vulnerable to the race-around problem when J=K=1 is held for an entire clock pulse.

Master-slave construction (Topic 8.5) is the standard fix for race-around in JK flip-flops.

JK flip-flops in classic counter and control-logic design

Before D flip-flops became the near-universal default in modern synchronous ASIC and FPGA design, JK flip-flops were extremely popular in TTL-era digital design specifically because the toggle behavior maps so directly onto binary counters — tying J and K together (J=K=T) produces exactly the T flip-flop from Topic 8.4, the natural building block for ripple and synchronous counters covered in Module 10. Classic ICs like the 7476 dual JK flip-flop were staples of mid-20th-century digital design for precisely this reason.

Circuit Symbol

IEEE block symbol for the JK flip-flop: J and K data inputs on the left, CLK with its clock-edge indicator, Q and Q' complementary outputs on the right — no invalid state, since J=K=1 toggles instead of racing.

Assuming any JK flip-flop implementation safely handles J=K=1 held for a long clock pulse, toggling exactly once per pulse.

Only edge-triggered or properly master-slave JK implementations guarantee exactly one toggle per clock pulse; a naive level-triggered design can toggle multiple times during a single high pulse (race-around).

The toggle behavior itself is well-defined logically, but the physical implementation matters enormously: level-sensitive feedback with J=K=1 held throughout the enable window can cause repeated, unpredictable toggling within what should be a single clock cycle.

[tricky-problem] How does the JK flip-flop resolve the forbidden-state problem present in a plain SR flip-flop? A. It removes the J=1,K=1 combination from the device entirely, making it an illegal input just like SR B. It redefines the J=1,K=1 combination as a well-defined toggle operation (Q flips to its complement), so every input combination now produces a valid, predictable next state C. It adds a third control input to disambiguate the forbidden case D. It ignores K entirely and behaves like a D flip-flop

B. It redefines the J=1,K=1 combination as a well-defined toggle operation (Q flips to its complement), so every input combination now produces a valid, predictable next state — JK removes the invalid SR combination in the classic implementation by giving the previously-forbidden case a clean, well-defined meaning: toggle. This is confirmed by the characteristic equation Q(next) = J·Q' + K'·Q, which evaluates to Q' (the complement) exactly when J=K=1 — a fully deterministic outcome, not an invalid one.

What new hazard does a naive level-triggered JK flip-flop implementation introduce, even though it has no forbidden input state? A. It cannot be reset asynchronously B. The race-around problem: if J=K=1 is held for the entire duration the clock is high, the output can toggle repeatedly and unpredictably within a single clock pulse C. It requires two separate clock signals to operate at all D. It cannot store a logic 0

B. The race-around problem: if J=K=1 is held for the entire duration the clock is high, the output can toggle repeatedly and unpredictably within a single clock pulse — Because a level-triggered device stays 'listening' for the whole high phase of the clock, and toggling changes Q which feeds right back into the same still-active gates, J=K=1 held throughout that window can cause multiple uncontrolled toggles instead of exactly one — the race-around problem, resolved by the master-slave architecture in Topic 8.5.

A JK flip-flop currently holds Q=0. It receives the following J,K pairs at four successive clock edges: (1,1), (1,0), (1,1), (0,1). Determine Q after each edge.

Edge 1: J=1,K=1 → toggle: Q goes 0→1. Edge 2: J=1,K=0 → set: Q stays 1. Edge 3: J=1,K=1 → toggle: Q goes 1→0. Edge 4: J=0,K=1 → reset: Q stays 0. Final Q sequence: 1, 1, 0, 0.

Apply the truth table (hold/reset/set/toggle) at each step, carrying Q forward from the previous step.