14.2 ADC: Analog-to-Digital Converter

Explain the three-stage process (sampling, quantization, encoding) an ADC uses to turn a continuous analog signal into a digital code, and identify the key specifications that describe its performance.

An Analog-to-Digital Converter (ADC) performs the reverse job of a DAC: it takes a continuous, infinitely-variable analog signal — a microphone voltage, a sensor reading, a temperature probe's output — and turns it into a digital code a processor can store, compute on, and transmit. Almost nothing in the physical world is naturally digital; light intensity, sound pressure, temperature, and voltage all vary continuously. An ADC is the mandatory gateway between that analog reality and any digital system that needs to reason about it, which is why ADCs sit at the front end of virtually every sensor interface, audio input, and measurement instrument. Because an ADC must approximate a continuous quantity using a finite number of discrete digital codes, it always involves some unavoidable loss of information — understanding exactly how and why that loss occurs is the core of this topic and the four that follow it (Resolution, Quantization, Sampling, and the specific ADC architectures).

The Three-Stage ADC Process

Every ADC, regardless of internal architecture, conceptually performs three distinct operations in sequence. Sampling captures the analog signal's instantaneous value at specific, regularly-spaced points in time, converting a signal that is continuous in time into a sequence of discrete-time snapshots (this is covered in depth in Section 14.5, including the Nyquist rate condition that governs how often those snapshots must be taken). Quantization then takes each sampled voltage — which is still a continuous analog value at the moment it's captured — and rounds it to the nearest one of a finite set of allowed digital levels (covered in depth in Section 14.4). Encoding is the final step: assigning a binary code (a specific bit pattern) to each quantized level so the result can be stored, processed, and transmitted digitally.

These three stages are logically separable even though a real ADC circuit often performs them together or overlapped in time. A sample-and-hold circuit typically performs the sampling stage by freezing an analog voltage steady during the conversion; the converter's internal comparison logic (which differs sharply between ADC architectures — successive approximation, flash, and dual-slope, as covered in Sections 14.6–14.8) performs the quantization; and an output register or encoder logic (such as a priority encoder converting a thermometer code to binary in a flash ADC) performs the encoding.

• Sampling — capture the analog value at discrete instants in time. • Quantization — round the captured value to the nearest allowed digital level. • Encoding — assign a binary code to each quantized level. • Different ADC architectures (SAR, flash, dual-slope) implement these three stages with very different circuits and very different speed/accuracy/cost trade-offs.

Key ADC Specifications

Resolution describes how many bits — and therefore how many distinct output codes, 2^N — the ADC uses to represent its full input range; it directly determines the smallest voltage difference the converter can distinguish (Section 14.3 covers this precisely). The reference voltage sets the full-scale input range the ADC is calibrated against: an input at or above Vref maps to the maximum output code, and the reference's own accuracy and stability directly limits the accuracy of every conversion, no matter how many bits the converter has.

Conversion time is how long the ADC takes to produce a valid digital output after a sample is captured, and it varies enormously by architecture — a flash ADC can convert in a single clock cycle, while a SAR ADC needs roughly N clock cycles for an N-bit result, and a dual-slope ADC can take thousands of clock cycles because it relies on two full integration phases. Conversion time, together with the sampling requirement, sets the maximum signal bandwidth the ADC can faithfully digitize.

• Resolution (N bits) → 2^N possible output codes. • Reference voltage → defines the full-scale analog input range. • Conversion time → how long one sample takes to become a valid digital code; varies drastically by architecture. • Sampling rate (1/sampling period) must satisfy the Nyquist condition for the input signal's bandwidth.

Practical and Real-World Applications

ADCs are the entry point for essentially every digital measurement and digital audio/video capture system: microphones feeding digital audio recorders, sensor front-ends in embedded systems (temperature, pressure, light), digital multimeters and oscilloscopes, and the receive chain of any digital communication system that must sample an incoming analog waveform. The choice of ADC architecture in a real design is driven directly by which specification matters most for the application — a digital multimeter favors the dual-slope ADC's noise rejection and accuracy over speed, while a high-speed oscilloscope or radio receiver favors the flash ADC's raw conversion speed, and a general-purpose sensor interface favors the SAR ADC's balance of moderate speed, good accuracy, and low power/cost.

The ADC pipeline

Sampling, quantization, and encoding are conceptually separate steps even when a real circuit performs them in an interleaved or overlapping way. Every real ADC introduces some combination of quantization error, timing/sampling error, and reference-related error.

Analog input x(t)
      │
      ▼
  [ Sample ]   (freeze value at time t = nTs)
      │
      ▼
  [ Quantize ]  (round to nearest of 2^N allowed levels)
      │
      ▼
  [ Encode ]    (assign N-bit binary code)
      │
      ▼
Digital output D[n]

Code Examples

The sample-and-hold stage freezes the input at 3.21 V at the chosen instant. Quantization finds the closest of the 256 allowed 8-bit levels to that voltage — level 164 — which necessarily discards the small difference between the true 3.21 V and the level's exact center value (this discarded difference is the quantization error discussed in Section 14.4). Encoding then represents 164 as the 8-bit binary pattern 10100100 that a digital system can store and process. Expected result: 10100100

3.21 V → nearest of 256 levels → code 164 → binary 10100100

Analog signal: x(t) — a smoothly varying voltage between 0 V and 5 V
Sample time:   t = 3 ms  →  captured value ≈ 3.21 V
Quantize:      8-bit ADC, Vref = 5 V, LSB ≈ 19.53 mV
               nearest code = round(3.21 / 0.01953) = 164
Encode:        164 (decimal) → 10100100 (binary)

Where ADC fits in a measurement system

An anti-alias low-pass filter typically precedes the sampling stage to remove signal content above the Nyquist limit before it can be aliased — see Section 14.5.

Sensor (analog) --> [ Anti-alias filter ] --> [ Sample & Hold ] --> [ ADC core ] --> Digital code --> Processor

Important Rules

Every ADC performs three logical stages: sampling (in time), quantization (in amplitude), encoding (into a binary code).

Resolution (bits) sets how many discrete output codes are possible: 2^N.

Conversion time varies drastically by architecture: flash is fastest, SAR is moderate, dual-slope is slowest but most noise-immune.

The reference voltage's own accuracy is a hard ceiling on the whole converter's accuracy, regardless of bit count.

Where ADCs show up

Digital audio recording, sensor data acquisition in embedded systems, digital multimeters and oscilloscopes, and the receive chains of digital radios and communication systems all depend on an ADC as their entry point from the analog world into digital processing.

Treating 'ADC' as a single monolithic technique, and assuming any ADC's speed, accuracy, and cost trade-offs are interchangeable with any other.

Match the ADC architecture to the application: SAR for balanced general-purpose use, flash for raw speed, dual-slope for high-accuracy/noise-immune measurement (like digital multimeters).

Sections 14.6–14.8 show that SAR, flash, and dual-slope ADCs implement the same three-stage sample/quantize/encode process with drastically different circuits, speeds, and hardware costs — the 'best' ADC is always application-dependent.

Put the three stages of ADC conversion in the correct order. A. Encode → Quantize → Sample B. Sample → Quantize → Encode C. Quantize → Sample → Encode D. Sample → Encode → Quantize

B. Sample → Quantize → Encode — An ADC first samples the analog signal at a discrete instant in time, then quantizes that captured value to the nearest allowed digital level, and finally encodes the chosen level as a binary code.

Why might a digital multimeter use a dual-slope ADC instead of a flash ADC, even though flash ADCs convert much faster? A. Dual-slope ADCs are cheaper to manufacture in every case B. Flash ADCs cannot handle DC voltages C. The multimeter prioritizes accuracy and noise rejection over speed, which favors the dual-slope architecture's integration-based measurement D. Dual-slope ADCs have higher resolution by definition

C. The multimeter prioritizes accuracy and noise rejection over speed, which favors the dual-slope architecture's integration-based measurement — Dual-slope ADCs integrate the input over a fixed time and can reject certain periodic noise (like mains hum) very effectively, at the cost of being much slower than flash conversion — exactly the trade-off a high-accuracy, low-speed instrument like a multimeter wants.

A 6-bit ADC has Vref = 2 V. An analog input of 1.5 V is sampled. Identify (a) how many total output codes the ADC can produce, and (b) roughly which decimal code the 1.5 V sample should quantize to.

(a) 2^6 = 64 total codes (0–63). (b) 1.5 V is 0.75 of the 2 V full scale; 0.75 × 64 ≈ 48, so the sample quantizes to approximately code 48.

Total codes = 2^N. For (b), compute the fraction 1.5/2 of full scale and multiply by the number of codes.