10.8 Ring Counter
Explain how a ring counter circulates a single one-hot bit through a feedback shift register, calculate its state count, and identify why it must be correctly initialized to function.
A ring counter is built by taking a shift register (Topic 9) and feeding its final serial output directly back around into its own serial input, closing the chain into a loop — hence 'ring.' It is normally initialized with exactly one flip-flop set to 1 and the rest to 0 (a one-hot pattern), and that single 1 bit then circulates around the ring, one position per clock, forever. It exists because many control and sequencing applications don't need a counter's binary value at all — they need a simple, cheaply-decoded 'we are now on step k' signal, and a ring counter provides exactly that, for free, directly from its flip-flop outputs.
Core concept: a shift register with its output looped back to its input
Structurally, a ring counter is identical to a SIPO or PIPO shift register (Module 9), with one addition: the output of the last stage (Q(n-1)) is wired directly back to the serial input of the first stage (D0), instead of that serial input coming from some external source. On every clock edge, the entire stored pattern shifts one position, exactly like any shift register, except that the bit which would otherwise be lost off the end reappears at the front instead — nothing is ever gained or lost from the ring, only rotated.
If the ring is initialized with a single 1 among all 0s (a one-hot pattern), that property is preserved by the shifting: each clock edge simply moves the single 1 one position further around the ring, and after exactly n clock edges (for an n-stage ring), the 1 has visited every stage exactly once and returned to its starting position, ready to repeat the cycle.
• A ring counter = a shift register (SIPO/PIPO style) with its last stage's output fed back into its first stage's input. • Initialized with a single 1 and the rest 0s (one-hot), that single 1 simply circulates, one position per clock. • For a 4-flip-flop ring counter: 1000 -> 0100 -> 0010 -> 0001 -> 1000 -> ... (repeats every 4 clocks).
Step-by-step working: state count and free decoding
This is the ring counter's key distinguishing property compared to a binary counter of the same width: an n-stage ring counter has exactly n usable, distinct states in its cycle — not 2^n. With 4 flip-flops, a binary counter offers 16 states, but a ring counter offers only 4 (1000, 0100, 0010, 0001) — the ring counter trades away most of the theoretically available state combinations (all the ones with zero, two, three, or four 1s set) in exchange for a state encoding that is dramatically simpler to work with.
That simplicity is the payoff: because each of the n valid states has exactly one bit set, and it's always a different bit, no decoding logic is needed at all to know which state the ring counter is currently in — each flip-flop's own Q output directly is the signal 'we are now in state k,' usable straight from the flip-flop with no AND gates or comparators required, unlike a binary counter, which needs a decoder to turn its encoded value into individual per-state signals.
Practical application, real-world use, and common mistake
Ring counters are the classic circuit for sequencer/timing-generator applications: driving a sequence of n independent, mutually-exclusive control pulses (one active at a time) directly from n flip-flop outputs with zero decoding logic, or the well-known 'Knight Rider' LED chaser effect, where each flip-flop's output directly lights one LED, and the single lit LED visibly walks along the row as the ring counter cycles.
The critical, and most common, mistake is forgetting that a ring counter's correct one-hot behavior depends entirely on correct initialization at power-up. Shift-register flip-flops have no inherent preference for any particular starting value, so an un-initialized ring counter can power up all-zero (in which case it simply circulates zero forever — a permanently 'stuck' ring, since a shift register with no 1s anywhere has nothing to shift around) or with more than one 1 set (in which case it circulates that invalid multi-hot pattern indefinitely, never self-correcting into a proper one-hot sequence on its own in a basic implementation). A real design must include an explicit preset pulse (forcing exactly one flip-flop to 1 and the rest to 0) at startup, or add extra self-correcting logic, rather than assuming the ring will find its way into a valid pattern by itself.
Ring counter notation
The ring counter's usable state count (n) is dramatically smaller than a binary counter's (2^n) using the same flip-flop count — this is the trade-off for its free, decode-less state signaling. Correct one-hot initialization (exactly one 1, all others 0) at power-up/reset is mandatory for correct operation.
n-stage ring counter (shift register with feedback):
D0 <---------------------------------------------\
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[FF0]--Q0-->[FF1]--Q1-->[FF2]--Q2-->[FF3]--Q3------/
(feedback: last stage's Q wired directly back to first stage's D)
All flip-flops share one CLK.
Number of valid (one-hot) states = n (NOT 2^n)
Example cycle, n = 4, starting from 1000:
1000 -> 0100 -> 0010 -> 0001 -> 1000 -> ... (period = 4 clocks)Code Examples
Exactly matching the spec's example: with 4 flip-flops initialized to 1000, the single 1 bit walks one position per clock — 1000, 0100, 0010, 0001 — and returns to 1000 on the 4th clock, giving a period of exactly n = 4 clocks. Only 4 distinct states are ever visited, not the 16 that 4 flip-flops could theoretically represent. Expected result: Q0, Q1, Q2, Q3 each pulse high for exactly one clock cycle per period, one at a time, in strict rotating order.
An n-stage ring counter visits exactly n distinct one-hot states before repeating — here, 4 states for 4 flip-flops.
Clock# Q3 Q2 Q1 Q0 Active output
0 1 0 0 0 Q0 = 1 (initialized state)
1 0 1 0 0 Q1 = 1
2 0 0 1 0 Q2 = 1
3 0 0 0 1 Q3 = 1
4 1 0 0 0 Q0 = 1 <- back to the starting state, cycle repeatsRing counter: closed-loop shift register
The last stage's output loops directly back into the first stage's input, closing the shift chain into a ring.
+----------------------------------------+
| |
v |
D0 -->[FF0]--Q0-->[FF1]--Q1-->[FF2]--Q2-->[FF3]--Q3
^ ^ ^ ^ ^
CLK (Q0 out) CLK (Q1 out) ... (all stages share CLK)Important Rules
An n-stage ring counter has exactly n usable one-hot states in its cycle, not 2^n — far fewer states per flip-flop than a binary counter, in exchange for zero-cost decoding.
No external decoding logic is needed to identify the current state — each flip-flop's own Q output is directly the 'we are in state k' signal, since exactly one bit is set at a time.
The ring counter must be initialized (via preset or a startup pulse) with exactly one 1 and the rest 0s — without correct initialization it can power up stuck at all-zero or circulating an invalid multi-hot pattern indefinitely.
Sequencers and LED chaser displays
Ring counters directly drive simple sequential-pulse-generator circuits — for example, a controller that must activate exactly one of several outputs at a time, in a fixed rotating order, with no decoding logic — and are the textbook circuit behind 'Knight Rider'-style chasing LED displays, where each ring-counter output bit drives one LED and the single lit LED visibly walks down the row as the ring cycles.
Powering up a ring counter and assuming it will settle into a correct one-hot circulating pattern on its own, with no explicit initialization.
Always include an explicit preset/initialization pulse that forces exactly one flip-flop to 1 and every other flip-flop to 0 before the ring counter begins normal operation, since a basic ring counter has no built-in mechanism to self-correct from an all-zero or multi-hot power-up state.
A shift register with feedback simply preserves whatever pattern it starts with, whether that pattern is a valid one-hot state or not — an all-zero ring just circulates zero forever (permanently stuck), and a multi-hot ring just circulates that same invalid pattern forever, so correct behavior absolutely depends on deliberate initialization, not on the circuit finding its own way there.
[conceptual] How many distinct, valid one-hot states does a ring counter built from n flip-flops have, and how does that compare to a binary counter with the same number of flip-flops? A. 2^n states, the same as a binary counter B. n states — dramatically fewer than the 2^n states a same-size binary counter offers C. n^2 states D. Exactly 1 state, since it just repeats the same value
B. n states — dramatically fewer than the 2^n states a same-size binary counter offers — A ring counter only ever visits its n one-hot patterns (one 1, n-1 zeros, in every rotation) — it deliberately does not use any of the other 2^n - n combinations a binary counter of the same width could represent. This is a large trade-off in state-count efficiency, made worthwhile by the ring counter's need for zero decoding logic.
[interview] Why must a ring counter be explicitly initialized with exactly one flip-flop set to 1 before it can operate correctly? A. Because ring counters require a special initialization clock that runs faster than the main clock B. Because a shift register with feedback simply preserves whatever pattern is already present when it starts running — an all-zero or multi-hot starting pattern will just circulate as-is indefinitely, with no built-in mechanism in a basic ring counter to correct itself into a valid one-hot state C. Because ring counters cannot function with fewer than 8 flip-flops D. It is not actually necessary — ring counters always self-correct within one clock cycle
B. Because a shift register with feedback simply preserves whatever pattern is already present when it starts running — an all-zero or multi-hot starting pattern will just circulate as-is indefinitely, with no built-in mechanism in a basic ring counter to correct itself into a valid one-hot state — A ring counter's feedback shift register has no logic that inspects or corrects its own pattern — it simply rotates whatever bits are already stored. If it powers up all-zero, it circulates zero forever (stuck); if it powers up with more than one 1, it circulates that invalid pattern forever. Correct one-hot operation is only guaranteed by an explicit preset/initialization step, not by any inherent self-correcting property of the basic design.
You need a sequencer that activates exactly one of 5 control outputs at a time, cycling through all 5 in a fixed repeating order, with the simplest possible decoding logic. Would a 5-stage ring counter or a Mod-5 binary counter (needing 3 flip-flops plus a decoder) be the better fit, and why?
A 5-stage ring counter is the better fit here: it uses 5 flip-flops (more than the Mod-5 binary counter's 3) but needs zero decoding logic at all, since each of its 5 outputs is already directly the 'active now' signal for one control output. The Mod-5 binary counter uses fewer flip-flops but requires 5 separate 3-input decode gates (one per state) to generate the same 5 individual control signals — for a small number of outputs where decode-logic simplicity matters more than flip-flop count, the ring counter is the standard choice.
Compare flip-flop count versus decoding logic complexity for each option.