1.3 Logic Levels: VIL, VIH, and the Undefined Region
Describe how real digital devices define LOW and HIGH using voltage thresholds rather than exact values, and explain why voltages in the undefined region are electrically unsafe to interpret.
Logic 0 and logic 1 are mathematical abstractions, but real digital circuits are built from transistors operating on continuously variable voltages. Logic levels are the electrical specification that bridges this gap: a set of voltage ranges that a device guarantees will be reliably interpreted as LOW or HIGH, plus a threshold structure that defines exactly where those ranges begin and end. Understanding logic levels is what separates treating digital logic as pure Boolean math from understanding it as a physical, electrical system with real tolerances and failure modes.
Input and output thresholds
Every digital device specifies four key threshold voltages in its datasheet: VOL(max), the highest voltage the device guarantees to output for a logic LOW; VOH(min), the lowest voltage it guarantees to output for a logic HIGH; VIL(max), the highest input voltage the device is guaranteed to still recognize as LOW; and VIH(min), the lowest input voltage the device is guaranteed to recognize as HIGH.
A device is guaranteed to correctly read LOW for any input voltage below VIL(max), and correctly read HIGH for any input voltage above VIH(min). These 'output' and 'input' thresholds are deliberately not symmetric — output guarantees are tighter (closer to the rails) than input requirements, which is precisely what creates a safety margin, discussed below.
The undefined region
Between VIL(max) and VIH(min) lies a band of voltages the device makes no guarantee about — the undefined (or forbidden/transition) region. A voltage that falls in this band cannot safely be assumed to be either a 0 or a 1: the device's actual response is unspecified, may vary between individual chips, may vary with temperature or supply voltage, and in some technologies can even cause excess current draw or oscillation.
This is a crucial distinction from pure Boolean algebra, where a variable is simply 0 or 1 with nothing in between: threshold specifications belong to the electrical interface of a device, not to Boolean mathematics itself. Correct digital design ensures that every signal, under all specified operating conditions, either stays below VIL(max) or above VIH(min) and only passes through the undefined region briefly during a clean, fast transition — never settles there.
Noise margin
Noise margin is the voltage 'cushion' between what one stage guarantees to output and what the next stage requires to correctly read that value. The low noise margin is VIL(max) minus VOL(max); the high noise margin is VOH(min) minus VIH(min). This cushion is the maximum amount of unwanted noise a signal can pick up on the wire between two devices and still be interpreted correctly.
Because the exact threshold voltages depend on the logic family and specific device (as noted directly in the specification), noise margins differ between logic families (this is elaborated further in Module 12 — Logic Families). The general principle established here, though, is universal: reliable digital communication depends on maintaining a real voltage gap between 'guaranteed output' and 'required input' at every connection.
Logic-level threshold notation
The exact numeric values of VIL, VIH, VOL, VOH depend on the logic family/device — the spec deliberately leaves these as symbols, not fixed numbers, because they differ (e.g., between TTL and CMOS, and between supply voltages). A well-designed digital system never intentionally leaves a signal sitting in the undefined region; that region is only ever transiently crossed during a fast, clean edge.
LOW -> below VIL(max)
HIGH -> above VIH(min)
UNDEFINED (forbidden) region -> between VIL(max) and VIH(min)
Output guarantees:
VOL(max) -- highest voltage guaranteed for a LOW output
VOH(min) -- lowest voltage guaranteed for a HIGH output
Noise margin:
NML = VIL(max) - VOL(max)
NMH = VOH(min) - VIH(min)Code Examples
Any input voltage above VIH(min) is guaranteed to be read as HIGH; any input voltage below VIL(max) is guaranteed to be read as LOW. A voltage that lands between those two thresholds falls in the undefined band and the device's response is not specified.
A voltage strictly between VIL(max) and VIH(min) cannot be safely assumed to be 0 or 1.
Supply rail (HIGH): ------------------ e.g. 5 V or 3.3 V
HIGH region
------------------ VIH(min)
UNDEFINED region
------------------ VIL(max)
LOW region
Ground (LOW): ------------------ 0 VLogic-level bands from ground to supply
A device's supply rail is split into three bands by its input thresholds; only the outer two bands have a defined logical meaning.
VDD -------------------------- logic HIGH (guaranteed above VIH(min))
HIGH region
VIH(min) ----------------------
UNDEFINED / forbidden region
VIL(max) ----------------------
LOW region
GND -------------------------- logic LOW (guaranteed below VIL(max))Important Rules
LOW is any voltage below VIL(max); HIGH is any voltage above VIH(min); the band between them is undefined.
VOL(max) and VOH(min) are the device's own output guarantees; VIL(max) and VIH(min) are what it requires of an incoming signal.
Noise margin = the gap between an output guarantee and the next stage's input requirement; it is the tolerable noise budget on a connection.
Threshold values are part of a device's electrical specification (datasheet), not a universal constant — they vary by logic family and device.
A signal must never be relied upon to settle in the undefined region; correct design keeps signals in the LOW or HIGH band except during brief transitions.
Where this shows up
Interfacing two chips from different logic families or supply voltages — for example, a 3.3 V microcontroller talking to a 5 V peripheral — is fundamentally a logic-levels problem: the designer must verify that the 3.3 V device's VOH(min) is comfortably above the 5 V device's VIH(min), and that the 5 V device's VOL(max) is below the 3.3 V device's VIL(max), or add level-shifting hardware. Getting this wrong is one of the most common causes of unreliable communication between mismatched digital components.
Treating an input voltage that is 'close enough' to the supply rail or ground as automatically valid, without checking it against the actual VIL/VIH thresholds.
Compare the measured or specified voltage explicitly against the device's datasheet VIL(max) and VIH(min) values before concluding it will be read as a clean LOW or HIGH.
A voltage in the undefined region cannot safely be assumed to be either 0 or 1 — the device's actual behavior there is unspecified and can vary chip-to-chip, with temperature, or with supply voltage. Only a rigorous comparison against the datasheet thresholds (not a visual guess) establishes a signal's guaranteed logic value.
[tricky] Why can't a voltage in the undefined region simply be rounded to whichever threshold it is closer to? A. Because the device's actual response in that region is unspecified and not guaranteed by the manufacturer, regardless of which threshold the voltage is numerically closer to B. Because the undefined region does not physically exist in real circuits C. Because rounding is only valid for analog signals, not digital ones D. Because VIL and VIH are always equal in every logic family
A. Because the device's actual response in that region is unspecified and not guaranteed by the manufacturer, regardless of which threshold the voltage is numerically closer to — Threshold specifications are part of the electrical interface of a device, not merely Boolean mathematics. A voltage in the undefined region has no guaranteed interpretation — the device's real response can vary between individual parts, with temperature, and with supply voltage, so it cannot be safely assumed to be either 0 or 1.
[interview] What is noise margin, and why does it matter in a real digital design? A. The difference between a device's clock frequency and its maximum rated frequency B. The voltage cushion between a driving stage's guaranteed output level and a receiving stage's required input threshold, representing the tolerable noise budget on the connection C. The number of gates a signal can pass through before it degrades D. A measure of how loud a circuit's audible switching noise is
B. The voltage cushion between a driving stage's guaranteed output level and a receiving stage's required input threshold, representing the tolerable noise budget on the connection — Noise margin (NML = VIL(max) - VOL(max), NMH = VOH(min) - VIH(min)) quantifies how much unwanted noise a signal can accumulate on a wire between two devices and still be reliably interpreted at the receiving end. Larger noise margins make a design more robust against real-world electrical noise.
A device specifies VIL(max) = 0.8 V and VIH(min) = 2.0 V on a 5 V supply. Classify each of these input voltages as LOW, HIGH, or UNDEFINED: 0.3 V, 1.4 V, 3.0 V, 0.8 V exactly.
0.3 V -> LOW (below 0.8 V). 1.4 V -> UNDEFINED (between 0.8 V and 2.0 V). 3.0 V -> HIGH (above 2.0 V). 0.8 V -> LOW (at the VIL(max) boundary, which is defined as the guaranteed-LOW limit).
Remember the boundary values themselves belong to the guaranteed LOW/HIGH regions as stated (below/above), and everything strictly between VIL(max) and VIH(min) is undefined.