2.8 1's Complement: Bit Inversion and the Dual-Zero Problem

Compute the 1's complement of a binary number by bit inversion, and explain why 1's complement representation produces both a +0 and a -0.

1's complement is a signed-number representation formed by simply inverting every bit of a number's unsigned binary pattern: every 0 becomes a 1, and every 1 becomes a 0. It is the conceptual stepping stone toward 2's complement (the following topic and the scheme actually used in nearly all modern hardware), and understanding its single well-known flaw — a duplicate representation of zero — is exactly what motivates 2's complement's extra '+1' step.

The bit-inversion rule

The rule for 1's complement could not be simpler: to find the 1's complement of a binary number, invert every bit — change each 0 to a 1 and each 1 to a 0. This is precisely the operation performed by a NOT gate applied independently to every bit of a binary word, which is why 1's complement is trivially cheap to implement in hardware (a bank of inverters, with no carry propagation needed at all).

Applying 1's complement to a positive number's binary representation produces the bit pattern digital hardware uses to represent that number's negative counterpart in a 1's-complement signed system — for example, in an 8-bit system, the 1's complement of +5 (00000101) is 11111010, which represents -5.

The dual-zero problem

The defining weakness of 1's complement is that it produces two distinct bit patterns that both represent zero: an all-zero pattern (00000000 in 8 bits) representing +0, and an all-one pattern (11111111) representing -0, since the 1's complement of all-zero bits is all-one bits. Mathematically, +0 and -0 are the same value, but a 1's-complement system cannot avoid encoding them as two different bit patterns.

This dual-zero problem is more than a curiosity — it complicates arithmetic hardware and comparison logic (a circuit must special-case two different bit patterns that both mean 'zero'), and it wastes one bit pattern that could otherwise represent a useful number. This single flaw is the primary reason 2's complement, which resolves it, became the dominant standard instead of 1's complement.

1's complement rule

1's complement inversion is implemented in hardware as a bank of independent NOT gates, one per bit, with no carry chain required. 1's complement of 1's complement returns the original number (applying the inversion twice cancels out).

1's complement: invert every bit

  0 -> 1
  1 -> 0

Code Examples

Each bit of 10100110 is independently flipped: the 1s become 0s and the 0s become 1s, position by position, producing 01011001. No carry or arithmetic is involved — this is a purely bitwise operation.

1's complement of 10100110 is 01011001

10100110
   |  (invert every bit)
   v
01011001

Two bit patterns for zero in 1's complement (4-bit)

1's complement's all-zero and all-one patterns both mean 'zero', which is the representation's core weakness.

+0:  0000
-0:  1111   (1's complement of 0000)

Both represent the value zero, but they are
two DIFFERENT bit patterns -- the dual-zero problem.

Important Rules

1's complement is formed by inverting every bit of the number (0 becomes 1, 1 becomes 0).

1's complement is implemented purely by independent bitwise inversion — no carry propagation is needed.

1's complement produces two distinct zero patterns: all-zeros (+0) and all-ones (-0), which is its key drawback.

Applying 1's complement twice returns the original value.

Where this shows up

1's complement is rarely used today for general-purpose signed integers, but it survives in specific protocols — notably the checksum calculation used in the Internet Protocol (IP) and TCP/UDP headers, which is explicitly defined using 1's-complement addition (including its 'end-around carry' rule), precisely because 1's complement's properties (like the ease of bitwise inversion) suit checksum verification well.

Treating +0 and -0 in a 1's-complement system as if they must always compare or behave identically in every piece of logic without special handling.

Recognize that 1's-complement systems require explicit extra logic (or an end-around carry adjustment) to correctly treat the two zero patterns as equal, precisely because they are numerically bit-different despite representing the same value.

1's complement has both +0 and -0 — a subtlety that must be explicitly accounted for in comparator and arithmetic circuit design, and is exactly the flaw that led to 2's complement's dominance, since 2's complement has only a single, unambiguous zero pattern.

[tricky] What is the defining drawback of 1's-complement signed representation? A. It cannot represent negative numbers at all B. It produces two distinct bit patterns that both represent zero (+0 and -0), complicating comparison and arithmetic logic C. It requires more bits than sign-magnitude for the same range D. It cannot be implemented using logic gates

B. It produces two distinct bit patterns that both represent zero (+0 and -0), complicating comparison and arithmetic logic — 1's-complement has both +0 (all zeros) and -0 (all ones), since inverting the all-zero pattern produces the all-one pattern. This dual representation of the same numeric value is the specific flaw that 2's complement was designed to eliminate.

[interview] Why is 1's complement cheap to implement in hardware compared to arithmetic operations like addition? A. Because it requires a full carry-propagate adder circuit B. Because it is a purely bitwise operation — each bit is inverted independently by its own NOT gate, with no dependency on neighboring bits or any carry chain C. Because 1's complement circuits use analog components D. Because it only applies to even numbers

B. Because it is a purely bitwise operation — each bit is inverted independently by its own NOT gate, with no dependency on neighboring bits or any carry chain — Unlike addition, which requires carry to propagate from each bit position to the next, 1's complement inversion operates independently on each bit — a simple bank of NOT gates suffices, with zero interaction or delay dependency between bit positions.

Find the 1's complement of the 8-bit binary number 01110001, and state what decimal value the original bit pattern and its 1's complement each represent under a 1's-complement signed interpretation.

1's complement of 01110001 is 10001110. The original, 01110001, has MSB=0 so it directly reads as positive: 64+32+16+1 = 113, i.e., +113. Its 1's complement, 10001110, represents -113 in an 8-bit 1's-complement system.

Invert every bit; the original pattern's MSB is 0, so it is a straightforward positive magnitude.