12.2 CMOS: Complementary MOS Logic

Explain why CMOS gates draw almost no static current, compute dynamic power from the Pdynamic ≈ αCV²f relationship, and reason about the voltage-squared power/speed trade-off.

CMOS (Complementary Metal-Oxide-Semiconductor) is the logic family that underlies essentially every modern digital IC — microprocessors, FPGAs, memory, and the 74HCxx logic families. Its defining idea is complementary pairs: every gate is built from a PMOS pull-up network and an NMOS pull-down network wired so that, for any valid input combination, exactly one of the two networks conducts and the other is off. This is what makes CMOS dramatically more power-efficient than bipolar TTL, and it is why CMOS became the technology every process node scaling story (and every mobile-device battery-life story) is built around.

Core concept: complementary pull-up and pull-down

In a CMOS inverter, a single PMOS transistor sits between VDD and the output, and a single NMOS transistor sits between the output and ground, with their gates tied together to the input. When the input is LOW, the PMOS turns on and the NMOS turns off, pulling the output HIGH through the PMOS; when the input is HIGH, the NMOS turns on and the PMOS turns off, pulling the output LOW. In both steady states, one transistor is fully off, so essentially no DC path exists from VDD to ground — the defining property that gives CMOS its near-zero static power draw compared to TTL.

More complex CMOS gates (NAND, NOR, AND-OR-INVERT) generalize this into pull-up and pull-down *networks* of series/parallel PMOS and NMOS transistors, built so the pull-down network is the exact logical complement of the pull-up network — wherever the pull-down conducts, the pull-up doesn't, and vice versa, for every input combination. This complementary structure is what keeps the 'no static current path' property true for arbitrarily complex CMOS gates, not just inverters.

Static vs dynamic power — and the V² relationship

Static power in CMOS isn't literally zero in real devices — subthreshold leakage current through the 'off' transistor grows more significant as processes shrink below roughly 90 nm, and is one of the central challenges in modern low-power IC design. But for most teaching purposes and for older/larger process nodes, static power is treated as negligible compared to the dominant term: dynamic power, dissipated every time a node actually switches and its parasitic capacitance is charged or discharged.

The spec's simplified dynamic-power relationship is Pdynamic ≈ α·C·V²·f, where C is the switched capacitance of the node, V is the supply voltage, f is the clock (or switching) frequency, and α is the activity factor — the fraction of clock cycles in which that node actually transitions (a node that toggles every cycle has α=1; one that rarely changes has a small α). The V² term is the headline fact of this formula: dynamic power scales with the *square* of supply voltage, so halving the supply voltage cuts dynamic power to roughly a quarter — which is exactly why aggressive voltage scaling (running chips at the lowest voltage that still meets timing) is the single biggest lever mobile and battery-powered CMOS designs pull to save power.

Noise immunity and the danger of a floating CMOS input

CMOS logic thresholds scale with the supply rail rather than being fixed at TTL's 0.8 V/2.0 V — a typical CMOS gate switches somewhere near the midpoint of VDD, giving it noise margins that scale up as VDD increases, generally wider than TTL's at the same supply. This is one reason 74HC-series CMOS parts are often preferred over 74LS-series TTL parts in electrically noisy environments (see the Noise Margin lesson for the numbers).

Unlike a TTL input, a floating CMOS input is genuinely dangerous rather than convenient. Because a CMOS gate input is essentially just the gate terminal of a MOSFET — extremely high impedance, drawing almost no DC current — a floating input has no defined voltage at all; it drifts to whatever value stray capacitance and leakage settle it at, often somewhere in the middle of the logic swing. A mid-swing input can turn *both* the PMOS and NMOS of the following stage partially on simultaneously, creating a direct 'shoot-through' or 'crowbar' current path from VDD to ground that can dramatically increase power draw, cause the input stage to oscillate, and in extreme or sustained cases contribute to device damage or latch-up. Every unused CMOS input must be tied firmly to VDD or ground (or to a defined logic signal) — never left floating.

Dynamic power formula

This is the single most quoted formula in low-power digital design — it is the mathematical reason 'lower the voltage' beats 'lower the frequency' for power savings, cycle-for-cycle.

Pdynamic ≈ α · C · V² · f

  α = activity factor (fraction of cycles the node switches, 0..1)
  C = switched (load) capacitance at the node, farads
  V = supply voltage, volts
  f = clock/switching frequency, Hz

Halving V  → Pdynamic drops to ~1/4
Halving f  → Pdynamic drops to ~1/2
Halving α  → Pdynamic drops to ~1/2

Code Examples

Plugging the four parameters straight into Pdynamic ≈ αCV²f gives about 2.18 mW dissipated by this node. If the supply were dropped to 1.65 V (half) with everything else unchanged, V² would drop to a quarter of its original value, so Pdynamic would fall to roughly 0.545 mW — a quarter of the original power for the same switching activity.

Pdynamic ≈ 2.18 mW at 3.3V; ≈0.545 mW at 1.65V — a 4× drop from a 2× voltage drop.

Given: C = 10 pF, V = 3.3 V, f = 100 MHz, α = 0.2

Pdynamic ≈ α · C · V² · f
         = 0.2 × (10×10⁻¹²) × (3.3)² × (100×10⁶)
         = 0.2 × 10×10⁻¹² × 10.89 × 100×10⁶
         = 0.2 × 10.89 × 1×10⁻³
         ≈ 2.18 × 10⁻³ W  = 2.18 mW

Important Rules

In steady state, a properly-formed CMOS gate has exactly one of its pull-up/pull-down networks conducting — never both, never neither.

Dynamic power dominates CMOS power draw at most process nodes; it scales with the square of supply voltage.

Static (leakage) power, though small per transistor, becomes a first-order design concern at deep-submicron process nodes.

Every unused CMOS input must be tied to a defined logic level — a floating CMOS input risks shoot-through current and oscillation.

Why voltage scaling dominates mobile chip design

Every modern mobile SoC uses Dynamic Voltage and Frequency Scaling (DVFS) — lowering both supply voltage and clock frequency together when full performance isn't needed. Because dynamic power scales with V² but only linearly with f, cutting voltage delivers a much bigger power win per unit of performance sacrificed than cutting frequency alone, which is precisely the Pdynamic ≈ αCV²f relationship in action, and is the reason chip designers push operating voltage as low as timing closure allows rather than only throttling clock speed.

Assuming CMOS draws essentially zero power under all conditions because 'CMOS has no static power.'

Account for dynamic power (αCV²f) at operating frequency, plus leakage on modern small-geometry processes.

The 'CMOS is low power' reputation refers specifically to static (DC, non-switching) power being much lower than bipolar families. Every clock cycle that switches a node still dissipates real dynamic power, and that dynamic term is usually the dominant power draw in an active CMOS system.

Tricky problem: why does reducing supply voltage cut CMOS dynamic power so much more effectively than reducing clock frequency by the same factor? A. Voltage has no real effect on power; only frequency matters B. Pdynamic ≈ αCV²f is linear in frequency but quadratic in voltage, so a given percentage cut in V produces a much larger percentage cut in power than the same percentage cut in f C. Lower voltage increases the activity factor, which lowers power D. Frequency and voltage always scale by the same factor, so there's no difference

B. Pdynamic ≈ αCV²f is linear in frequency but quadratic in voltage, so a given percentage cut in V produces a much larger percentage cut in power than the same percentage cut in f — The formula Pdynamic ≈ αCV²f has V raised to the second power but f only to the first, so a 2× reduction in voltage yields a 4× reduction in power, whereas a 2× reduction in frequency yields only a 2× reduction — this asymmetry is exactly why aggressive voltage scaling is the primary power-saving lever in CMOS design.

Why is a floating (unconnected) input dangerous specifically on a CMOS gate, but comparatively benign on a TTL gate? A. CMOS inputs are current-driven, so no current means no defined state at all B. A CMOS input is a high-impedance MOSFET gate with no defined resting voltage, so it can settle mid-swing and turn on both the PMOS and NMOS of the next stage simultaneously, causing shoot-through current — TTL's multi-emitter input structure instead defaults a floating input to a HIGH condition C. CMOS gates are physically smaller and more fragile than TTL gates D. Floating inputs only matter at high frequency, and CMOS always runs faster than TTL

B. A CMOS input is a high-impedance MOSFET gate with no defined resting voltage, so it can settle mid-swing and turn on both the PMOS and NMOS of the next stage simultaneously, causing shoot-through current — TTL's multi-emitter input structure instead defaults a floating input to a HIGH condition — TTL's bipolar input structure gives a floating input a well-defined (if not recommended) HIGH behavior. CMOS inputs are essentially open MOSFET gate capacitors with no DC bias path, so a floating CMOS input can sit at an indeterminate voltage — often near the switching threshold — which can turn on both halves of a complementary pair downstream and draw excess shoot-through current, exactly why unused CMOS inputs must always be tied to a defined rail.

A node has C = 5 pF and switches with activity factor α = 0.5 at f = 200 MHz on a 1.2 V supply. Compute Pdynamic, then recompute it if the design instead ran at 2.4 V and 100 MHz (same total 'work rate' in a loose sense) — which configuration draws more dynamic power, and by roughly how much?

Case 1 (1.2V, 200MHz): P = 0.5×5e-12×(1.2)²×200e6 = 0.5×5e-12×1.44×200e6 ≈ 7.2×10⁻⁴ W = 0.72 mW. Case 2 (2.4V, 100MHz): P = 0.5×5e-12×(2.4)²×100e6 = 0.5×5e-12×5.76×100e6 ≈ 1.44×10⁻³ W = 1.44 mW. Doubling voltage while halving frequency still draws about 2× the dynamic power, because V² (4×) outweighs the frequency being halved (0.5×), net 2× — confirming that voltage reduction is the more powerful lever than frequency reduction for a fixed amount of 'work.'

Compute Pdynamic ≈ αCV²f for each case and compare; remember V² dominates the comparison.