12.1 TTL: Transistor-Transistor Logic

Explain how TTL builds logic gates from bipolar junction transistors, state its standard voltage levels, and reason about its speed/power trade-offs across subfamilies.

TTL (Transistor-Transistor Logic) is a bipolar logic family — the '7400 series' — in which every gate is built from BJTs (bipolar junction transistors) rather than field-effect transistors. It was the workhorse logic family from the 1960s through the 1980s and is still the reference point most textbooks use for defining 'standard' logic levels (0.8 V / 2.0 V thresholds, a 5 V supply). Even though most modern designs use CMOS, TTL matters because (a) huge amounts of legacy and industrial hardware still uses 74LS-series parts, (b) TTL-compatible ('TTL levels') is still the phrase engineers use to describe a 5 V, 0.8/2.0 V threshold interface even on CMOS parts (74HCT is CMOS internally but TTL-compatible on its inputs), and (c) understanding TTL's internal structure explains *why* floating TTL inputs behave differently from floating CMOS inputs — a classic interview trap.

Core concept: how a TTL gate is built

A classic TTL NAND gate uses a multi-emitter input transistor: each emitter corresponds to one gate input. If any input is pulled to a valid LOW voltage, its emitter junction conducts and steals base current away from the transistor, which pulls the following stage LOW-driving; only when *every* input is HIGH does the multi-emitter transistor stop conducting through its emitters and instead push current into the base of the next stage, eventually driving the output. This structure is what makes the multi-emitter transistor a direct physical AND function on the inputs, inverted by the stages that follow to produce NAND — the reason NAND was TTL's cheapest, fastest native gate and the reason so many textbook problems reduce everything to NAND-NAND form.

The output stage of a standard TTL gate is a 'totem-pole' — an upper (pull-up) transistor and a lower (pull-down) transistor stacked so that one actively sources current when the output is HIGH and the other actively sinks current when the output is LOW. This gives TTL a genuinely low output impedance in both states (good drive strength, fast transitions into a load), but it also means a brief moment during switching where both transistors conduct partially, causing a current 'spike' — a contributor to TTL's comparatively higher power consumption and to supply-rail noise that decoupling capacitors are used to absorb.

Standard voltage levels and subfamilies

Standard TTL defines its logic levels against a nominal 5 V supply: VIL(max) = 0.8 V (any input below this is guaranteed to be read as LOW), VIH(min) = 2.0 V (any input above this is guaranteed to be read as HIGH), VOL(max) = 0.4–0.5 V (worst-case guaranteed output LOW), and VOH(min) = 2.4 V (worst-case guaranteed output HIGH). These numbers are the textbook reference values used throughout digital electronics whenever a problem says 'assume standard TTL levels.'

Because straight bipolar transistors driven into deep saturation are slow to come back out of saturation (stored-charge / turn-off delay), TTL split into several subfamilies trading speed against power: standard TTL (74xx), low-power TTL (74Lxx, slower but far less power), high-speed TTL (74Hxx, faster but more power), Schottky TTL (74Sxx, uses Schottky clamping diodes across the base-collector junction so transistors never fully saturate, giving much faster switching), and low-power Schottky (74LSxx) — the most widely used TTL subfamily in practice because it combines Schottky speed with low power draw. Later advanced Schottky (74ASxx) and advanced low-power Schottky (74ALSxx) pushed both axes further.

• Standard TTL (74xx): baseline speed and power • 74Lxx (low power): slower, much lower Icc • 74Hxx (high speed): faster, higher Icc • 74Sxx (Schottky): fast via non-saturating BJTs • 74LSxx (low-power Schottky): fast AND low power — the practical default

The floating-input quirk

Because of the multi-emitter input transistor structure, a TTL input that is left unconnected (floating) behaves electrically as if it were HIGH — the open emitter simply doesn't sink base current, which is the same condition as tying that input to a valid HIGH. This is a genuinely useful (if risky-to-rely-on) property, and it is the opposite of what happens on a CMOS input (covered in the CMOS lesson), where a floating input is dangerous rather than convenient. Relying on this behavior in production designs is still discouraged: floating inputs are far more susceptible to noise pickup, and a floating TTL input can behave inconsistently across manufacturing lots and temperature, so unused inputs should still be tied to a defined level through a resistor.

Standard TTL DC specifications (5 V supply)

These are the values used to compute noise margin (12.5) and fan-out (12.4) — memorize them, they recur across the module.

VIL(max) = 0.8 V   // max input voltage guaranteed read as LOW
VIH(min) = 2.0 V   // min input voltage guaranteed read as HIGH
VOL(max) = 0.4 V   // worst-case guaranteed output LOW (0.5 V on some parts)
VOH(min) = 2.4 V   // worst-case guaranteed output HIGH

Standard unit load (74xx):
  IIH = 40 µA   (input current drawn when driven HIGH)
  IIL = -1.6 mA (input current sunk when driven LOW)
  IOH = -400 µA (max output source current)
  IOL = 16 mA   (max output sink current)

Code Examples

The digits after '74' (00 here) identify the logic function and pinout — it is identical across every row. The letters in between identify the process/subfamily, which only changes the speed/power/level characteristics, never the truth table.

Same function number ⇒ same truth table; different letters ⇒ different speed/power trade-off.

74LS00  → Quad 2-input NAND, Low-power Schottky
74S00   → Same logic function, Schottky (faster, more power)
74H00   → Same logic function, High-speed TTL
74L00   → Same logic function, Low-power TTL (slow, thrifty)
74HCT00 → CMOS internally, but TTL-compatible input thresholds

Important Rules

Standard TTL levels: VIL(max)=0.8V, VIH(min)=2.0V, VOL(max)=0.4–0.5V, VOH(min)=2.4V on a 5V rail.

A saturating BJT output stage is inherently slower to turn off than a non-saturating one — this is why Schottky clamping exists.

A floating TTL input reads as HIGH due to the multi-emitter input transistor, but should never be relied on in production designs.

74LSxx (low-power Schottky) is the de-facto standard TTL subfamily for new/legacy-compatible designs.

Where TTL still shows up

Pure bipolar 74xx/74Sxx parts are largely obsolete for new designs, but 74LS-series parts remain in huge volumes of legacy industrial equipment, test gear, and hobbyist/educational kits, and the phrase 'TTL-level' or 'TTL-compatible' is still used every day to describe any 5 V logic interface with 0.8 V/2.0 V thresholds — including 74HCT (CMOS-process) parts specifically built to be pin- and level-compatible replacements for old TTL parts in mixed-family boards.

Leaving unused TTL inputs floating because 'TTL floats HIGH anyway.'

Tie unused TTL inputs to VCC (through a resistor) or to a used input of the same gate.

Floating inputs are more susceptible to noise coupling from adjacent switching signals and can behave inconsistently across parts and temperature; the 'floats HIGH' behavior is a side effect of the internal structure, not a specification you should design against.

Why does the Schottky (74Sxx / 74LSxx) TTL subfamily switch faster than standard 74xx TTL? A. It uses a higher supply voltage B. Schottky clamping diodes prevent the BJTs from fully saturating, so there is no stored-charge turn-off delay C. It has fewer logic levels to distinguish D. It replaces the totem-pole output with an open-collector output

B. Schottky clamping diodes prevent the BJTs from fully saturating, so there is no stored-charge turn-off delay — A Schottky clamp diode across the base-collector junction diverts excess base drive before the transistor saturates. A non-saturated BJT has no stored minority charge to remove when turning off, so it switches off far faster than a deeply saturated one — the core mechanism behind every 'S' TTL subfamily.

A TTL NAND gate input is left unconnected. What logic level does it electrically behave as, and why? A. LOW, because unconnected pins default to 0V B. Undefined/random, exactly like a CMOS input C. HIGH, because the open emitter of the multi-emitter input transistor can't sink base current, the same condition as a valid HIGH input D. It oscillates at the gate's propagation frequency

C. HIGH, because the open emitter of the multi-emitter input transistor can't sink base current, the same condition as a valid HIGH input — The multi-emitter input transistor only pulls the gate toward its LOW-output condition when an emitter is actively driven to a valid LOW voltage. An open (floating) emitter can't do that, so the transistor behaves as though that input were HIGH — a structural quirk of bipolar TTL, not something CMOS shares.

Interview question: give one concrete reason TTL generally dissipates more static power per gate than CMOS. A. TTL gates always run at a higher clock frequency B. TTL's bipolar totem-pole and internal resistor networks conduct some current in steady state regardless of output level, while CMOS's complementary pull-up/pull-down pair keeps one side fully off in each steady state C. TTL uses more logic gates per function D. TTL requires a negative supply rail

B. TTL's bipolar totem-pole and internal resistor networks conduct some current in steady state regardless of output level, while CMOS's complementary pull-up/pull-down pair keeps one side fully off in each steady state — CMOS's whole efficiency advantage comes from having a PMOS pull-up and NMOS pull-down where, in each steady logic state, one of the pair is essentially off — so almost no DC current flows except leakage. TTL's bipolar stages and internal bias resistors carry meaningful quiescent current in both states, which is the fundamental reason bipolar logic families draw more static power than CMOS at the same logic function.

A microcontroller GPIO outputs true CMOS levels on a 5 V rail (VOH(min) = 4.4 V, VOL(max) = 0.5 V). It must drive the input of a standard 74LS TTL gate. Is a level-shifter needed? Justify using the voltage numbers.

No level shifter is needed in this direction: the CMOS driver's VOH(min)=4.4V comfortably exceeds the TTL VIH(min)=2.0V, and its VOL(max)=0.5V is safely below the TTL VIL(max)=0.8V, so the TTL gate reliably reads both logic levels. The problematic direction is the reverse — a TTL output (VOH(min)=2.4V) driving a CMOS input that may require VIH(min) well above 2.4V, which is exactly why 74HCT-style CMOS-with-TTL-thresholds parts exist.

Compare the driver's guaranteed output levels against the TTL receiver's required input thresholds (VIH(min)=2.0V, VIL(max)=0.8V) — driving 'more ideal' levels into a TTL input is generally fine; the risky direction is TTL driving CMOS.