12.6 Propagation Delay: tPLH, tPHL, and Average tPD

Define tPLH and tPHL precisely, compute average propagation delay, and explain why gate delays are usually asymmetric.

Propagation delay is the time between a gate's input transitioning and its output responding to that transition. It is the single most important number for timing closure in digital design — every clock period budget is ultimately built by summing propagation delays along the longest logic path — and logic-family and loading choices (TTL vs CMOS, fan-out, wire capacitance) directly determine how large it is. This lesson focuses on the two directional delay numbers, tPLH and tPHL, and how they combine into the single 'tpd' figure datasheets often quote.

Core concept: two delays, not one

Because a gate's pull-up path and pull-down path are usually built from different types or numbers of transistors (recall the CMOS NAND/NOR asymmetry from the fan-in lesson), the delay for an output transitioning LOW-to-HIGH is generally not identical to the delay for HIGH-to-LOW. tPLH is defined as the propagation delay measured from the triggering input transition to the moment the output crosses its 50% point on its way from LOW to HIGH. tPHL is the mirror-image measurement for the output transitioning from HIGH to LOW. Datasheets specify both separately, along with their own individual min/typical/max values, because a design that only checks one of the two can miss a genuine timing violation happening on the other edge direction.

The commonly quoted single-number 'average propagation delay' collapses these two directional numbers into one figure for quick estimation: tpd ≈ (tPLH + tPHL)/2. This average is useful for back-of-envelope budget estimates across many gates in a path, but any rigorous timing analysis (like static timing analysis in ASIC/FPGA design) always tracks tPLH and tPHL separately per gate and per edge direction, because the worst-case path for a setup-time check might be dominated by one direction while the worst-case path for a hold-time check is dominated by the other.

What determines the delay's size

For a given gate, propagation delay grows with output loading — more fan-out or more parasitic wire/input capacitance means more charge/discharge time for the output node, directly increasing both tPLH and tPHL (recall the CMOS RC-style argument from the fan-out lesson). It also depends on the gate's own internal drive strength: a gate built with wider transistors can source/sink more current and switch a given load faster, at the cost of more silicon area and more input capacitance presented to whatever drives *it* — a trade-off repeated at every stage of a design.

Logic family also matters: bipolar TTL gates historically had propagation delays dominated by transistor storage-time effects (worse when saturated, better with Schottky clamping, as covered in the TTL lesson), while CMOS gate delay is dominated by the RC charge/discharge time of the switched capacitance — which is why CMOS delay estimates lean so heavily on load capacitance and drive strength rather than on saturation/storage-time arguments.

Propagation delay definitions

tPLH = delay, triggering input edge → output 50% point, LOW→HIGH transition
tPHL = delay, triggering input edge → output 50% point, HIGH→LOW transition

tpd ≈ (tPLH + tPHL) / 2      // average propagation delay

Code Examples

The gate's average propagation delay is 7 ns, but note this is only an average — a design that specifically needs the worst case for a critical HIGH-to-LOW transition should use 6 ns... actually the larger of the two values for worst-case margin, since 'worst case' means the longer delay, not the average. Always check which number a timing question is actually asking for.

tpd ≈ (8+6)/2 = 7 ns average; worst-case single-direction delay here is 8 ns (tPLH), not the average.

Given: tPLH = 8 ns,  tPHL = 6 ns

tpd ≈ (tPLH + tPHL) / 2
    = (8 + 6) / 2
    = 7 ns

Important Rules

tPLH and tPHL are measured from the triggering input edge to the output's 50% crossing point, one per transition direction.

tpd ≈ (tPLH + tPHL)/2 is a convenient average, not a substitute for tracking both directions in rigorous timing analysis.

Propagation delay increases with output loading (fan-out, wire/input capacitance) and decreases with stronger drive transistors.

The worst-case delay for a timing path is the larger of tPLH/tPHL relevant to that path's actual transition direction — never assume the average is conservative enough.

Critical-path timing closure

In any synchronous digital design, the maximum usable clock frequency is bounded by the longest combinational path's total propagation delay (sum of each gate's tPLH/tPHL along that path, whichever direction the actual signal transitions take) plus flip-flop setup time, all of which must fit within one clock period. Static timing analysis tools used throughout ASIC and FPGA design flows compute exactly this sum, per path, per edge direction, which is why understanding tPLH/tPHL as separate quantities — not just a single averaged number — is foundational to real timing closure work.

Assuming tPLH always equals tPHL for a real gate, or using the average tpd as if it were the guaranteed worst-case delay.

Look up (or measure) tPLH and tPHL separately, and use whichever direction is relevant — and its own max value — for worst-case timing analysis.

Real gates are built from asymmetric pull-up/pull-down structures (different transistor types, sometimes different sizing), so tPLH and tPHL are rarely identical. Using an average when a specific worst-case bound is required can silently underestimate the true delay on the slower-transitioning edge.

Why do rigorous timing tools track tPLH and tPHL separately instead of just using the averaged tpd everywhere? A. Because datasheets never actually specify tpd directly B. Because the worst-case timing path for a setup-time check may be dominated by one transition direction, and a different path (or a hold check) may be dominated by the other — averaging can hide the true worst case for either C. Because tPLH and tPHL are always identical, so tracking both is redundant but required by convention D. Because tpd only applies to sequential circuits, never combinational ones

B. Because the worst-case timing path for a setup-time check may be dominated by one transition direction, and a different path (or a hold check) may be dominated by the other — averaging can hide the true worst case for either — Different signal paths transition in different directions, and a gate's two directional delays are frequently unequal. A timing analysis that only used the average could underestimate the delay on whichever direction is actually slower for a given path, silently missing a real timing violation.

Tricky problem: a circuit passes a Boolean-equivalence check (its simplified form matches the truth table) but fails timing simulation with an unexpected output glitch. What propagation-delay-related fact explains this? A. Boolean simplification is always wrong and should never be trusted B. Different logic paths through the circuit can have different total propagation delays even when the simplified Boolean expression is logically correct, so signals can arrive at a common point at different times and cause a transient glitch before settling to the correct steady-state value C. The circuit must have a manufacturing defect D. Propagation delay only matters for sequential circuits, so this glitch is unrelated to gate delay

B. Different logic paths through the circuit can have different total propagation delays even when the simplified Boolean expression is logically correct, so signals can arrive at a common point at different times and cause a transient glitch before settling to the correct steady-state value — Boolean algebra proves steady-state equivalence — it says nothing about the relative timing of different physical paths. Two logically-equivalent paths reconverging at a gate can arrive at different times because of differing accumulated tPLH/tPHL along each path, producing a transient glitch even though the final settled output is logically correct — this is exactly the hazard mechanism explored in Module 13.

A 3-gate combinational path has these delays: Gate1 tPLH=4ns/tPHL=3ns, Gate2 tPLH=5ns/tPHL=6ns, Gate3 tPLH=2ns/tPHL=4ns. If the signal at the path's input makes a single transition that causes Gate1's output to go LOW→HIGH, Gate2's output to then go HIGH→LOW, and Gate3's output to then go LOW→HIGH, what is the total path delay for this specific transition sequence?

Gate1 transitions LOW→HIGH: use tPLH=4ns. Gate2 transitions HIGH→LOW: use tPHL=6ns. Gate3 transitions LOW→HIGH: use tPLH=2ns. Total path delay = 4 + 6 + 2 = 12 ns. Using the averaged tpd for each gate instead (4, 5.5, 3 → 12.5ns) would have given a different, less accurate number — real timing analysis always uses the actual directional delay per gate per transition, not the average.

Pick the matching directional delay (tPLH or tPHL) for each gate based on what that specific gate's output actually does, then sum them — do not use the average tpd here.