13.5 Hazards: Static and Dynamic

Classify static-1, static-0, and dynamic hazards, explain their cause (reconvergent unequal-delay paths), and design a hazard-free SOP expression using a consensus term.

A hazard is the potential for a combinational circuit to produce a momentary, incorrect output pulse during a single input transition, even though the circuit's Boolean function is logically correct in every steady state before and after the transition. Hazards exist because real gates have nonzero, and generally unequal, propagation delays — two different signal paths derived from the same changing input can arrive at a common downstream gate at slightly different times, and during that brief window the output can dip or spike to the wrong value before settling to the correct, logically-guaranteed final result.

The three hazard types

A static-1 hazard occurs when the output is supposed to remain steadily at 1 across an input transition, but momentarily glitches down to 0 before returning to 1. A static-0 hazard is the mirror image: the output should remain steadily at 0, but momentarily spikes up to 1. A dynamic hazard occurs when the output is supposed to make a single, clean transition (either 0→1 or 1→0) but instead glitches multiple times before settling at its correct final value (e.g., 0→1→0→1 instead of a clean 0→1) — dynamic hazards generally require at least three levels of logic with multiple reconverging paths of different lengths, making them somewhat less common to encounter than static hazards in simple two-level SOP/POS circuits.

All three share the same underlying mechanism: reconvergent fan-out with unequal path delay. A single input signal fans out to feed two or more different logic paths (e.g., two different product terms in an SOP expression, one of which includes that input true and another which includes its complement), those paths reconverge at a common gate (e.g., the final OR gate combining the SOP terms), and because the two paths have different accumulated propagation delays (different numbers of gates, different gate loading, different wire lengths), they don't change their contribution to the reconverging gate's output at exactly the same instant — creating the brief window where the output can be wrong even though its final, settled value is correct.

Worked case: a static-1 hazard in SOP form and its fix

Consider F = AB' + BC, and examine what happens when B transitions while A=1 and C=1 are held constant. Before the transition (B=0): AB' = A·1 = 1 (since B'=1), so F=1 via the AB' term. After the transition (B=1): BC = 1·1 = 1, so F=1 via the BC term. The function's steady-state value is 1 both before and after — F should ideally stay at a clean, steady 1 throughout the transition. But if the AB' term's path turns off (as B rises, making B'=0) slightly *before* the BC term's path turns on (as B rises, enabling B·C), there is a brief window where neither product term is asserted, and the OR gate's output momentarily dips to 0 — a static-1 hazard, caused entirely by the two paths' unequal delay in responding to the same B transition, even though the function is logically supposed to stay at 1 throughout.

The classic fix, derived from the Boolean consensus theorem, is to add a redundant 'consensus' term that covers exactly the transition the two original terms don't jointly cover: for F = AB' + BC, the consensus term is AC (the consensus of AB' and BC with respect to B). The hazard-free form becomes F = AB' + BC + AC. When A=1 and C=1 (the condition under which the hazard occurred), the AC term is asserted as 1 throughout the entire B transition, regardless of whether AB' has already turned off or BC has already turned on — bridging the gap and guaranteeing the OR gate always has at least one input at 1 during the transition, eliminating the momentary dip to 0. This generalizes into a standard K-map design rule: to build a hazard-free SOP realization, every pair of adjacent 1-cells that could be affected by a single-variable transition must be covered by at least one common product-term grouping in the chosen cover, even if that grouping is 'redundant' from a pure minimization standpoint.

Hazard types and the consensus-term fix

Static-1 hazard: output should stay 1, glitches to 0 momentarily
Static-0 hazard: output should stay 0, glitches to 1 momentarily
Dynamic hazard:  output should transition once cleanly, glitches multiple times

Hazard-free SOP rule:
  every pair of adjacent 1-cells (differing in one variable) must be
  covered by a common product term in the chosen K-map grouping

F = AB' + BC         (has a static-1 hazard on B, with A=C=1)
F = AB' + BC + AC    (hazard-free; AC is the consensus term)

Code Examples

Because AC depends only on A and C — both held constant during this transition — it provides a rock-solid 1 input to the final OR gate for the entire duration of the B transition, structurally guaranteeing the output can never dip to 0 regardless of any delay mismatch between the AB' and BC paths.

The consensus term AC is unaffected by the transitioning variable B, so it bridges the gap and eliminates the static-1 hazard.

F = AB' + BC + AC,  A=1, C=1, B transitioning 0→1

AC = 1·1 = 1   (constant, unaffected by B at all)

→ F = (AB') + (BC) + 1 = 1, regardless of the relative timing
  of the AB' and BC terms turning off/on

The OR gate always sees at least the AC input at 1 during the
transition, so F cannot glitch to 0 no matter how the other two
terms' delays compare.

Static-1 hazard: F = AB' + BC during a B transition (A=C=1)

Adding the consensus term AC keeps at least one OR input asserted throughout the transition, removing the momentary glitch.

B:      __/‾‾‾‾‾‾‾‾  (B rises from 0 to 1)
AB':    ‾‾\______   (turns off shortly after B rises)
BC:     ______/‾‾   (turns on shortly after B rises, but slightly later)
F(no fix): ‾‾\__/‾‾ (glitches to 0 in the gap — static-1 hazard)
AC (consensus): ‾‾‾‾‾‾‾‾‾‾ (stays 1 throughout, since A=C=1)
F(with AC fix): ‾‾‾‾‾‾‾‾‾‾ (stays cleanly at 1 — hazard eliminated)

Important Rules

Static-1 hazard: output should stay 1, momentarily glitches to 0. Static-0 hazard: mirror image, output should stay 0, momentarily glitches to 1.

Dynamic hazard: output should transition cleanly once, but glitches multiple times before settling — needs 3+ logic levels with unequal reconverging paths.

All hazards arise from reconvergent fan-out: one input feeding two+ paths with unequal delay that reconverge at a common gate.

Hazard-free SOP design rule: cover every pair of adjacent 1-cells (that a single-variable transition could affect) with a shared product term, even if redundant for minimization.

Where hazards actually matter

In a fully synchronous design where a combinational signal only feeds the data input of a flip-flop that samples it well after the logic has settled (satisfying setup time), a brief mid-cycle glitch is usually harmless — the flip-flop only cares about the value at the clock edge, long after any hazard has resolved. Hazards become a real functional bug specifically when a combinational, potentially-glitchy signal drives something asynchronous or edge-sensitive directly — an asynchronous clock, set, or reset input on a flip-flop, or the clock input of a ripple counter — where even a brief unwanted transition can be mistaken for a legitimate edge and corrupt state (this connects directly to the Glitches and Synchronization lessons that follow).

Assuming that proving F = AB' + BC + AC is Boolean-equivalent to F = AB' + BC (which it is, by the consensus theorem) means the extra AC term is pointless and safe to drop for a 'more minimal' implementation.

Recognize that the AC term, while logically redundant for steady-state truth-table equivalence, is functionally necessary to eliminate the transient static-1 hazard — minimality and hazard-freedom are different goals that can conflict.

This is precisely the tricky point carried over from the spec's propagation-delay lesson: Boolean simplification proves steady-state logical equivalence, not transient (glitch-free) equivalence. A minimized expression can be logically correct and still hazardous; a hazard-free design sometimes deliberately keeps 'redundant' terms.

What is the fundamental cause of a static-1 hazard in a two-level SOP circuit? A. The circuit's Boolean function is logically incorrect B. A single input transition affects two different product terms whose paths to the final OR gate have unequal propagation delay, so the two terms don't hand off their '1' contribution at exactly the same instant, creating a brief window where the OR gate momentarily sees all inputs at 0 C. The circuit has too few logic gates to implement the function correctly D. Static hazards only occur in sequential circuits, never in purely combinational ones

B. A single input transition affects two different product terms whose paths to the final OR gate have unequal propagation delay, so the two terms don't hand off their '1' contribution at exactly the same instant, creating a brief window where the OR gate momentarily sees all inputs at 0 — The function's logic is entirely correct (F=1 both before and after the transition) — the hazard is a purely transient, timing-driven effect caused by the two product terms (each responsible for asserting F=1 on one side of the transition) not overlapping in time due to unequal path delays, momentarily leaving neither term asserted.

Interview question: a colleague says 'I proved my simplified Boolean expression is logically equivalent to the original truth table, so my circuit is definitely glitch-free.' What's wrong with this reasoning? A. Nothing — logical equivalence always guarantees glitch-free behavior B. Boolean equivalence only guarantees the circuit produces the correct steady-state output for every input combination; it says nothing about the transient behavior during a single input transition, where unequal path delays between reconverging terms can still cause a hazard even in a logically-correct, minimized circuit C. The colleague's expression must contain a logic error if a hazard exists D. Hazards only occur in circuits with more than 10 gates

B. Boolean equivalence only guarantees the circuit produces the correct steady-state output for every input combination; it says nothing about the transient behavior during a single input transition, where unequal path delays between reconverging terms can still cause a hazard even in a logically-correct, minimized circuit — This is exactly the spec's own tricky-problem framing carried through the module: 'Boolean simplification proves logical equivalence in steady state; it does not automatically prove glitch-free timing behavior.' A perfectly minimized, logically-correct SOP expression can still have a static or dynamic hazard because minimization and hazard-elimination are different, sometimes conflicting, design goals.

F = A'C + AB has a static-1 hazard when A transitions with B=1 and C=1 held constant. Find the consensus term and write the hazard-free expression.

The two terms are A'C and AB, sharing the transitioning variable A (as A' in one, A in the other). Their consensus term is formed from the remaining literals: C (from A'C) ANDed with B (from AB), giving BC. The hazard-free expression is F = A'C + AB + BC. Checking: with B=1 and C=1 held constant, BC = 1 regardless of A's transition, so the OR gate always has at least one asserted input throughout the A transition, eliminating the static-1 hazard exactly as the AC term did in the worked example above.

The consensus of two terms that share a variable (here A, appearing as A' in one term and A in the other) is formed by ANDing together the *other* literals from each term.