16.2 Verilog Boolean Operators: Expressing Gate Logic Directly

Translate a Boolean algebra expression (NOT, AND, OR, XOR, XNOR) directly into a Verilog bitwise expression, and correctly predict how that expression behaves bit-by-bit on multi-bit signals.

Boolean algebra and Karnaugh-map simplification, covered earlier in this course, produce a simplified sum-of-products or product-of-sums expression on paper. Verilog's bitwise operators are the direct, one-to-one bridge from that paper expression to synthesizable hardware: every gate you've studied — NOT, AND, OR, XOR, XNOR — has exactly one corresponding Verilog operator, and a simplified Boolean equation can usually be typed into an assign statement almost unchanged. This lesson is a focused tour of that operator set: what each symbol means, how operator precedence affects a multi-operator expression, and how these operators behave once signals stop being single wires and become multi-bit buses.

The Core Operator Set and What Each One Means

Verilog gives each of the fundamental gate functions its own bitwise operator: ~ for NOT (inversion), & for AND, | for OR, ^ for XOR, and ~^ (or equivalently ^~) for XNOR. Each of these operates bit-by-bit: for a binary operator like &, bit 0 of the result comes from ANDing bit 0 of each operand, bit 1 of the result from ANDing bit 1 of each operand, and so on — exactly as if you had drawn one physical gate per bit position and wired the buses straight into them.

There is no separate bitwise NAND or NOR operator in the language, because they are trivially expressed by composing NOT with AND or OR — ~(a & b) for NAND, ~(a | b) for NOR — which is itself a useful thing to internalize: Verilog's operator set mirrors the minimal, composable nature of Boolean algebra rather than trying to give every named gate its own dedicated symbol.

• ~a — bitwise NOT (inversion) of a. • a & b — bitwise AND. • a | b — bitwise OR. • a ^ b — bitwise XOR (1 where the bits differ). • a ~^ b (or a ^~ b) — bitwise XNOR (1 where the bits match).

Operator Precedence and Why Parentheses Matter

Like most C-family languages, Verilog defines a precedence order among its operators, and & binds tighter than |, which in turn is distinct from ^/~^. In the module's own worked example, assign y = (a & b) | c;, the parentheses around a & b are not strictly required by precedence rules — & already evaluates before | — but writing them explicitly is standard practice in RTL code, because it makes the intended grouping unambiguous to a human reader without forcing them to recall the full precedence table.

This matters more than it might seem: an incorrectly grouped Boolean expression synthesizes into genuinely different hardware — a different gate topology, not just a stylistic difference — so a misplaced or missing parenthesis is a functional bug, not a cosmetic one. The safest habit, especially while learning, is to parenthesize every sub-expression of more than one operator explicitly rather than relying on memorized precedence.

From K-Map Result to Verilog Expression

The practical payoff of this operator set is that a minimized sum-of-products expression from a Karnaugh map translates almost mechanically into a single assign statement: each product term (AND of literals) becomes an & group, each inversion becomes a ~, and the sum (OR) across product terms becomes | joining the groups. For example, a K-map-simplified expression like F = A'B + AC becomes assign f = (~a & b) | (a & c); with essentially no restructuring needed.

This direct correspondence is exactly why RTL design is taught right after Boolean algebra and K-maps in this course's roadmap — the mental model doesn't change, only the notation does. A designer who can simplify a truth table by hand can, with this operator vocabulary, immediately express that simplification as synthesizable hardware.

Bitwise vs. Logical: A Recurring Distinction

Just as & differs from && (covered in 16.1), | differs from ||: | is bitwise OR, producing a per-bit result the width of its operands, while || is logical OR, collapsing each operand to a single true/false value and producing one bit. The same distinction applies across the board — bitwise operators build hardware gate structures directly, while logical operators build single-bit true/false tests, which are appropriate in a conditional (if (a || b)) but not as a description of gate-level hardware.

A reliable rule of thumb while learning: if you are describing what a wire or bus should be driven with (an assign right-hand side meant to represent gate logic), reach for the bitwise operators (~ & | ^ ~^). If you are writing a yes/no condition to control branching (inside an if, covered later with procedural blocks), the logical operators (! && ||) are usually what's intended.

The Full Bitwise Boolean Operator Set

All five base operators are bitwise: applied independently, per bit position, across the full width of their operands. ~^ and ^~ are interchangeable spellings of the same XNOR operator. Parenthesize sub-expressions explicitly in mixed &/|/^ expressions — it costs nothing and removes any ambiguity for the reader.

~a        // NOT
a & b     // AND
a | b     // OR
a ^ b     // XOR
a ~^ b    // XNOR  (also written a ^~ b)

// Composed gates (no dedicated operator needed):
~(a & b)  // NAND
~(a | b)  // NOR

Code Examples

This is the module's own worked example. (a & b) builds the AND term first (grouped explicitly with parentheses, even though & already has higher precedence than |), and | c ORs that term with c. Read left to right, the expression states the Boolean equation directly: y is true whenever both a and b are true, or whenever c is true, matching a two-level AND-then-OR gate structure exactly.

assign y = (a & b) | c;

XOR (^) is the natural 'difference detector' between two bits: it outputs 1 exactly when its inputs disagree, which is why XOR gates appear at the heart of adders and comparators throughout this course. XNOR (~^) is its exact complement — an 'equality detector' that outputs 1 exactly when the two bits match, useful for building bit-by-bit equality comparators. Expected result: diff = a XOR b; equal = a XNOR b — and diff is always the bitwise inverse of equal for the same inputs.

assign diff = a ^ b;

module sop_example (
    input  wire a,
    input  wire b,
    input  wire c,
    output wire y
);

// y = (a AND b) OR c
assign y = (a & b) | c;

endmodule

module compare_1bit (
    input  wire a,
    input  wire b,
    output wire diff,   // 1 if a and b differ
    output wire equal   // 1 if a and b match
);

assign diff  = a ^ b;
assign equal = a ~^ b;

endmodule

Important Rules

~ NOT, & AND, | OR, ^ XOR, ~^/^~ XNOR — the complete bitwise operator set; each operates per-bit across the full operand width.

NAND and NOR have no dedicated operator: compose them as ~(a & b) and ~(a | b).

& binds tighter than |; still parenthesize mixed expressions explicitly for readability and to avoid grouping mistakes.

Bitwise operators (~ & | ^) describe gate-level hardware; logical operators (! && ||) describe single-bit true/false tests for conditionals.

A minimized SOP Boolean expression maps almost mechanically to a single assign statement using these operators.

Parity and Error Checking

The XOR-based parity idea in the equality/difference example generalizes directly to real hardware: a chain of XOR gates across every bit of a byte computes its parity bit, which is exactly how simple error-detection schemes (like the parity bit covered earlier in this course's number-systems module) are implemented in memory controllers and communication links — ^ reduced across a whole bus is the standard Verilog idiom for it.

assign y = a | b || c; // mixing bitwise and logical OR in one expression assign y = a | b | c;

Mixing | and || in the same expression is legal syntax but almost never intended: || forces its operands to be treated as single true/false values, silently changing the meaning of a multi-bit sub-expression the moment any operand is wider than one bit. When building a gate-level Boolean expression, stay consistently in the bitwise operator family.

[interview] Why does Verilog not provide a dedicated NAND or NOR bitwise operator? A. Because NAND and NOR are trivially composed from the existing operators (~(a & b) and ~(a | b)), so a separate symbol would be redundant B. Because NAND and NOR gates cannot be synthesized from RTL code C. Because NAND and NOR only exist at the gate-level modeling layer, not in behavioral Verilog D. Because ~ cannot be applied to the result of & or |

A. Because NAND and NOR are trivially composed from the existing operators (~(a & b) and ~(a | b)), so a separate symbol would be redundant — Verilog's Boolean operator set mirrors the minimal composability of Boolean algebra itself: since any Boolean function can be built from NOT, AND, and OR, the language only needs operators for those (plus XOR/XNOR for convenience) — NAND and NOR are simply the inverted forms, expressed by wrapping ~ around & or |.

In the expression assign y = (a & b) | c;, why are the parentheses around a & b not strictly required? A. Because & has higher precedence than | in Verilog, so a & b is grouped first regardless of parentheses B. Because Verilog always evaluates expressions left to right with no precedence rules C. Because assign statements ignore parentheses entirely D. Because | is not a valid Verilog operator without a preceding &

A. Because & has higher precedence than | in Verilog, so a & b is grouped first regardless of parentheses — Verilog's operator precedence table places & above |, so a & b | c and (a & b) | c produce identical hardware. The parentheses are added purely for human readability — a strong convention in RTL code even when precedence rules would already produce the correct grouping.

[interview] What is the practical difference between | and || when both operands are 8-bit buses? A. | produces an 8-bit result (bitwise OR of each corresponding bit pair); || collapses each 8-bit bus to a single true/false value first and produces a 1-bit result B. They always produce identical results regardless of operand width C. || is only legal inside assign statements, while | is only legal inside if conditions D. | requires both operands to be the same width, while || does not

A. | produces an 8-bit result (bitwise OR of each corresponding bit pair); || collapses each 8-bit bus to a single true/false value first and produces a 1-bit result — This is the same bitwise-vs-logical distinction covered for & vs && in 16.1, applied to OR: | performs eight independent single-bit OR operations in parallel; || treats each entire 8-bit bus as 'zero' or 'nonzero' and produces one bit representing whether either bus is nonzero — a fundamentally different circuit.

Using only the bitwise operators from this lesson, write a single assign statement (inside a module with inputs a, b, c and output y) implementing the Boolean expression F = (A NAND B) OR (NOT C).

module nand_notc ( input wire a, input wire b, input wire c, output wire y ); assign y = (~(a & b)) | (~c); endmodule

Build the NAND sub-term as ~(a & b) first, build the ~c term next, then combine the two with | — parenthesize each sub-term explicitly.