13.1 Timing Diagrams: Reading Signal Behavior Over Time

Read a timing diagram to identify clock edges, sampling points, and the relationship between a clock signal and a data signal.

A timing diagram is a waveform-style drawing of one or more digital signals plotted against time, and it is the primary tool engineers use to reason about and verify a design's temporal behavior — when signals change relative to each other, which clock edge a value is meant to be sampled on, and whether a signal is stable during the windows other logic depends on. Every datasheet for a real chip (SPI/I2C peripherals, DRAM, microcontroller buses) publishes timing diagrams precisely because a truth table alone says nothing about *when* things happen — and 'when' is exactly what timing diagrams exist to capture.

Core concept: signals plotted against a shared time axis

A timing diagram places one signal per horizontal row (CLK, DATA, and any other control/status signals of interest), all sharing the same horizontal time axis, so a vertical slice through the diagram shows the state of every signal at that instant. Clock edges — the rising or falling transitions of the CLK trace — are the reference points the diagram is built around, because most digital logic is synchronous: state changes and data sampling happen only in relation to a specific, designated clock edge (rising-edge-triggered or falling-edge-triggered, per the design).

The spec's own example diagram — CLK: __/‾‾\__/‾‾\__, DATA: ___‾‾‾‾______, with an arrow marking the 'sample edge' — illustrates the core reading skill: locate the active clock edge (here, the rising edge marked by the arrow), then look at what DATA is doing at that exact instant. If DATA is stable and valid at the sample edge, the circuit correctly captures its value; the diagram is really answering the question 'what value gets latched in, and precisely when?'

Step-by-step: how to read one

First, identify the clock's period (the time between two consecutive identical edges) and its active edge type — rising or falling — since that determines every subsequent sampling instant in the diagram. Second, for each signal of interest, trace across the time axis to find its value at each active clock edge, not at arbitrary points in between; a signal's value halfway between two clock edges is usually irrelevant to a synchronous circuit's behavior. Third, check for setup and hold requirements around each active edge: does the data signal become stable *before* the edge (satisfying setup time) and remain stable *after* the edge (satisfying hold time)? A signal that changes too close to — or exactly at — the active edge is a timing violation risk, covered in depth in the setup/hold lessons (Module 7) and the race/hazard lessons later in this module.

Timing diagram vocabulary

Rising edge   — signal transitions LOW → HIGH
Falling edge  — signal transitions HIGH → LOW
Active edge   — the specific edge type (rising or falling) that the circuit reacts to
Period (T)    — time between two consecutive identical edges
Sample point  — the instant, at an active edge, where a signal's value is captured

Code Examples

Walking through the three-step reading process on the spec's own diagram: the marked sample edge is a rising CLK edge, and at that exact point DATA has already transitioned to and settled at HIGH, so a rising-edge-triggered flip-flop sampling DATA at this edge correctly captures a 1.

Only the signal's value exactly at the active clock edge matters for synchronous sampling — not its value between edges.

CLK:  __/‾‾\__/‾‾\__
DATA: ___‾‾‾‾______
          ↑
       sample edge

Reading order:
1. CLK's active edge is rising (marked ↑)
2. At that instant, DATA is already HIGH and stable
3. Therefore the circuit correctly samples DATA = 1 at this edge

Basic CLK/DATA sampling relationship

The rising edge marked with ↑ is the instant DATA's value is captured; DATA must be stable across the setup/hold window straddling that edge.

CLK:  __/‾‾\__/‾‾\__
DATA: ___‾‾‾‾______
          ↑
       sample edge

Important Rules

Always identify the active edge type (rising or falling) first — it determines every sampling instant in the diagram.

Only a signal's value at the active edge matters for synchronous capture, not its value elsewhere in the cycle.

A signal must be stable through the setup window before, and the hold window after, the active edge to be sampled reliably.

Timing diagrams are the standard way datasheets specify interface protocols (SPI, I2C, memory buses) — reading them correctly is a core hardware-interfacing skill.

Datasheet compliance

Every serial protocol datasheet (SPI, I2C, UART bit timing) publishes a timing diagram specifying exact minimum/maximum durations between edges, required setup/hold windows around sample points, and edge polarity conventions (clock idle state, active edge). Correctly interfacing custom hardware to any of these protocols starts with correctly reading that datasheet's timing diagram — a design that gets the active edge or sampling window wrong will misread data intermittently or entirely.

Reading a signal's value at an arbitrary point on the diagram (e.g., visually 'in the middle') instead of exactly at the active clock edge.

Locate the precise active edge instant and read every signal's value only at that instant for synchronous sampling analysis.

A signal can be transitioning, glitching, or simply irrelevant between active edges — synchronous logic only cares about the value present at the moment of the active edge, so reading anywhere else can give a completely wrong interpretation of what the circuit actually captures.

In the spec's CLK/DATA diagram, why is the specific point marked with an arrow ('sample edge') the only instant that matters for correctly capturing DATA? A. Because timing diagrams only ever show one relevant instant, by convention B. Because synchronous digital logic captures signal values specifically at the active clock edge, so DATA's value at any other point in the cycle is irrelevant to what gets stored C. Because DATA only has a defined value at that one instant and is undefined everywhere else D. Because the arrow indicates where the diagram's time axis begins

B. Because synchronous digital logic captures signal values specifically at the active clock edge, so DATA's value at any other point in the cycle is irrelevant to what gets stored — Edge-triggered synchronous elements (like flip-flops) sample their input only at the designated active clock edge. The rest of the waveform — how DATA behaves before or after that edge — matters only insofar as it must be stable through the setup/hold window surrounding that edge; the actual captured value is determined solely by DATA's state at the edge itself.

Interview question: a colleague hands you a chip's SPI timing diagram from its datasheet before you write any interfacing code. What is the single most important piece of information to extract first? A. The chip's part number printed in the diagram's title B. Which clock edge (rising or falling) is the active sampling edge, since every subsequent setup/hold and data-validity requirement in the diagram is defined relative to it C. The color scheme used to draw the diagram D. The total number of signals shown in the diagram

B. Which clock edge (rising or falling) is the active sampling edge, since every subsequent setup/hold and data-validity requirement in the diagram is defined relative to it — Every other detail in a timing diagram — setup/hold windows, valid data periods, protocol phase boundaries — is expressed relative to the active clock edge. Misidentifying which edge is active (a common SPI CPOL/CPHA mistake) causes every downstream interpretation of the diagram, and any code written from it, to be wrong.

Sketch (in ASCII, in words, or on paper) a CLK/DATA timing diagram where DATA changes value exactly at the same instant as the active rising clock edge, rather than well before it. What risk does this illustrate, and which upcoming topic does it foreshadow?

A diagram where DATA's transition edge lines up with (or occurs just before/after) CLK's rising edge shows a setup-time violation risk: the receiving flip-flop needs DATA to already be stable for some minimum time *before* the edge, and a DATA transition coincident with the edge gives it no such margin. This foreshadows the setup/hold timing concepts (Module 7) and directly motivates the race-condition and hazard topics later in this module, where simultaneous or near-simultaneous transitions are exactly what causes unpredictable circuit behavior.

Think about what 'stable before the edge' actually requires, and what happens if that requirement isn't met.