14.6 SAR ADC: Successive Approximation Register

Trace the binary-search conversion process of a SAR ADC bit by bit, and explain the roles of the sample-and-hold, internal DAC, comparator, and SAR logic blocks.

The Successive Approximation Register (SAR) ADC is one of the most widely used ADC architectures in general-purpose electronics, prized for striking a strong balance between conversion speed, resolution, power consumption, and circuit cost. Rather than comparing the input against every possible level at once (as a flash ADC does) or integrating it over time (as a dual-slope ADC does), a SAR ADC finds the correct digital code through an efficient binary search — testing one bit at a time, from the most significant bit down to the least significant bit, narrowing in on the answer the same way a person plays a 'guess the number' game by repeatedly halving the remaining range.

The Four Building Blocks

A SAR ADC is built from four cooperating blocks. A sample-and-hold circuit first captures and freezes the analog input voltage steady for the duration of the entire conversion, since the binary-search process takes multiple clock cycles and the input must not move during that time. An internal DAC (exactly the kind of converter covered in Section 14.1) generates a trial analog voltage corresponding to the SAR's current best guess at the digital code. A comparator checks whether the held input voltage is above or below that DAC's trial voltage, producing a single bit of information per comparison: 'the answer is higher' or 'the answer is lower.' The Successive Approximation Register (SAR) itself is the control logic that holds the code being built, decides which bit to test next, and updates the guess based on each comparator result.

These four blocks work together in a tight feedback loop: the SAR proposes a code, the internal DAC turns that code into a trial voltage, the comparator reports whether the held input is above or below that trial voltage, and the SAR updates its guess accordingly before moving to the next bit.

• Sample-and-hold — freezes the analog input steady for the whole conversion. • Internal DAC — converts the SAR's current guess into a trial analog voltage. • Comparator — reports whether the held input is above or below the trial voltage. • SAR logic — decides which bit to test next and accumulates the final digital code.

Binary-Search Conversion, MSB to LSB

The SAR tests bits from MSB toward LSB. Conversion begins by tentatively setting the most significant bit to 1 (with all other bits 0) and asking the comparator whether the held input is above or below the resulting trial voltage. If the input is above the trial voltage, that MSB is kept as 1 (the answer is at least that large); if the input is below, the MSB is reset to 0. Either way, the SAR then moves to the next bit, tentatively sets it to 1, and repeats the same above/below test — each successive bit only needs to be tested against a trial voltage that already reflects every higher bit's now-settled value.

This process continues one bit at a time until every bit position, down to the LSB, has been tested and settled, at which point the accumulated code is the finished digital output. Because exactly one bit is resolved per comparison cycle, an N-bit SAR conversion takes N clock cycles (plus, in a real device, a small amount of fixed overhead for sampling and output latching) — a direct, predictable relationship between resolution and conversion time that distinguishes SAR conversion from both the single-cycle flash ADC and the much slower, integration-based dual-slope ADC.

• One bit resolved per comparison cycle, from MSB down to LSB. • Each trial voltage reflects all previously-settled higher bits plus a tentative guess for the current bit. • An N-bit SAR conversion takes approximately N clock cycles. • This binary-search approach needs far less hardware than flash conversion, at the cost of being slower per sample.

Practical and Real-World Applications

SAR ADCs are the default choice for the vast majority of general-purpose microcontroller analog inputs, sensor interfaces, and data-acquisition systems, precisely because their conversion time scales linearly (not exponentially) with resolution, their power consumption is modest, and their comparator/DAC-based design achieves good accuracy without the massive comparator count a flash ADC would need at the same resolution. When an application needs moderate-to-high resolution (8 to 18 bits is common) at moderate sample rates (kilosamples to a few megasamples per second) with low power draw, a SAR ADC is almost always the starting point.

Code Examples

Each row tests exactly one bit while holding all higher, already-decided bits fixed. The SAR always tries setting the next bit to 1 first, checks the comparator result, and keeps that bit only if the held input is still above the resulting trial voltage — otherwise it resets that bit to 0 and moves on. After all four bits are tested, the accumulated code 1010 (decimal 10, corresponding to a 10 V trial level) is the closest representable level to the true 10.2 V input. Expected result: 1010

Four comparisons resolve four bits, one MSB-to-LSB decision per cycle.

Vin (held) = 10.2 V,  Vref = 16 V,  N = 4 bits  (LSB = 1 V)

Bit 3 (MSB): guess 1000 → trial = 8 V.  10.2 V > 8 V  → keep bit3 = 1
Bit 2:       guess 1100 → trial = 12 V. 10.2 V < 12 V → bit2 = 0
Bit 1:       guess 1010 → trial = 10 V. 10.2 V > 10 V → keep bit1 = 1
Bit 0 (LSB): guess 1011 → trial = 11 V. 10.2 V < 11 V → bit0 = 0

Final code: 1010  (decimal 10 → trial voltage 10 V, closest level to 10.2 V)

SAR ADC conversion loop

Each loop iteration tests one bit: the SAR proposes a trial code, the DAC converts it, the comparator says higher/lower, and the SAR updates the guess before moving to the next bit.

┌─────────────┐
Vin ──►│ Sample&Hold │──► held voltage
        └─────────────┘        │
                                ▼
                         ┌─────────────┐
         guess code ───► │ Internal DAC│──► trial voltage
              ▲           └─────────────┘        │
              │                                    ▼
              │                            ┌──────────────┐
              └──── update guess ◄──────────│  Comparator  │
                    (SAR logic)             └──────────────┘
                                        (held voltage vs trial voltage)

Important Rules

SAR ADC building blocks: sample-and-hold, internal DAC, comparator, SAR control logic.

Bits are tested from MSB to LSB, one bit resolved per comparison cycle.

An N-bit SAR conversion takes approximately N clock cycles.

SAR ADCs trade conversion speed (slower than flash) for far lower hardware cost than a flash ADC at the same resolution.

Where SAR ADCs show up

SAR ADCs are built into nearly every general-purpose microcontroller as the on-chip analog input peripheral, and are the workhorse converter for sensor front-ends, data-acquisition boards, and any application needing a good balance of resolution, speed, and low power consumption rather than the extremes of flash speed or dual-slope precision.

Assuming a SAR ADC tests bits in an arbitrary or LSB-first order.

Remember that SAR conversion always proceeds MSB first, narrowing the search range by half with each successive bit, exactly like a binary search.

The SAR tests bits from MSB toward LSB — testing the most significant bit first is what lets each subsequent comparison narrow the remaining uncertainty by half, giving the algorithm its efficient, predictable N-cycle conversion time.

In what order does a SAR ADC test the bits of the digital output code? A. Randomly, until the comparator settles B. LSB first, then progressively more significant bits C. MSB first, progressing down to the LSB D. All bits are tested simultaneously in one cycle

C. MSB first, progressing down to the LSB — The SAR tests bits from MSB toward LSB, using a binary-search strategy: each comparison against the internal DAC's trial voltage narrows the remaining search range by half, which only works correctly when starting from the most significant bit.

Which four blocks does a SAR ADC combine to perform its conversion? A. Two comparators and two DACs B. Sample-and-hold, internal DAC, comparator, and SAR control logic C. A resistor ladder, priority encoder, and clock only D. An integrator, a reference, and a counter

B. Sample-and-hold, internal DAC, comparator, and SAR control logic — A SAR ADC's coverage is sample-and-hold, DAC, comparator, and SAR — the sample-and-hold freezes the input, the internal DAC generates trial voltages for the SAR's current guess, the comparator reports above/below, and the SAR logic runs the bit-by-bit binary search.

An 8-bit SAR ADC runs its internal logic at a 1 MHz clock, using one clock cycle per bit decision. Approximately how long does one full conversion take, and what is the approximate maximum sample rate this implies?

8 bits × 1 μs/cycle (1/1 MHz) ≈ 8 μs per conversion, implying a maximum sample rate on the order of 1/8μs ≈ 125,000 samples per second, before accounting for any fixed sample-and-hold or output-latching overhead.

Conversion time ≈ N cycles at the clock period; sample rate ≈ 1 / conversion time (ignoring fixed overhead).