7.1 Combinational vs Sequential Logic: Adding Memory to Circuits
Correctly classify any digital circuit as combinational or sequential by identifying feedback paths and memory elements, and explain why sequential circuits require a clock.
Every digital circuit you have built so far in this course — gates, adders, multiplexers, decoders — has been combinational: its output at any instant depends only on the values present at its inputs right now. That model breaks down the moment a system needs to remember anything: a counter must recall how many pulses it has seen, a register must hold a value after the input that produced it has changed, and a CPU must track which instruction it is executing. Sequential logic is the half of digital design that adds memory to circuits, and understanding precisely where the line falls between "purely computes a function of current inputs" and "depends on its own history" is the single most important conceptual fork in this entire course — everything from Module 7 onward (latches, flip-flops, registers, counters, memory, and ultimately the CPU datapath) is built on this distinction.
Core Concept: The Defining Test Is Feedback, Not Complexity
A combinational circuit is a network of logic gates with no feedback loop: signals flow strictly from inputs to outputs, and at any given moment the outputs are a pure Boolean function of the current inputs — change an input, and (after gate propagation delay settles) the output updates to match, with no memory of what the inputs used to be. A multiplexer, adder, decoder, comparator, or any circuit built purely from AND/OR/NOT/XOR trees with a single forward-flowing signal path is combinational, no matter how large or complex the Boolean expression gets.
A sequential circuit is one whose output depends on both the current inputs and the circuit's internal state — and that state is what makes memory possible. Mechanically, sequential circuits always contain a feedback path: some output (or an internal node) is routed back and combined with the inputs, which is exactly what lets a circuit's present behavior depend on what happened to it in the past. Most (but not all) sequential circuits are also synchronous, meaning that feedback path is gated by a clock signal so state only changes at controlled, predictable moments rather than continuously chasing itself around the loop.
This is why the classification test is never about circuit size or gate count — a circuit with a thousand gates and zero feedback is still combinational, while a two-gate SR latch (a pair of cross-coupled NOR gates, covered fully in the next topics) is sequential the instant you connect its own output back into its own input.
• Combinational: output = f(current inputs only). No feedback. No memory. • Sequential: output = f(current inputs, current state). Feedback path exists. Has memory. • The presence of a loop routing a signal back into the circuit that produced it is the structural signature of a sequential circuit.
Step-by-Step: How to Classify an Unfamiliar Circuit
Given a schematic or an RTL block you have never seen, work through three checks in order. First, trace every output back toward the inputs and ask whether any wire loops back on itself — does an output (or a derived internal signal) ever feed back into an earlier stage of the same circuit? If yes, it is at minimum a candidate for sequential behavior. Second, look for explicit storage elements — latches, flip-flops, registers — which are themselves built from feedback internally, so a block instantiating any of them is sequential even if the surrounding glue logic is purely combinational. Third, check for a clock input; while not every sequential element is clocked (asynchronous latches are level-sensitive, not clocked), the presence of a clock pin is a strong, almost universal signal that the block holds state.
A common trap is a circuit that looks purely combinational at the gate level but is actually sequential because of a subtle unintended feedback loop — this happens constantly in real RTL when a designer forgets to assign an output on every path of an if/case block, and a synthesis tool infers a latch to hold the "remembered" previous value on the missing path. That inferred latch is a genuine sequential element, even though nobody intended to build one — this exact failure mode is explored fully in Topic 7.3.
• Step 1 — Trace for feedback: does any output loop back into the circuit's own input path? • Step 2 — Look for storage primitives: latches, flip-flops, registers, memory arrays. • Step 3 — Look for a clock pin (strong hint of sequential logic, though not proof by itself for asynchronous latches).
Practical Application: Why Real Systems Need Both
No real digital system is purely one or the other — a CPU's datapath is the canonical example of the two working together. The ALU (arithmetic logic unit) is combinational: give it two operands and an opcode, and it computes a result instantly (after propagation delay) with zero memory of the previous instruction. But that result has to go somewhere durable, or it is lost the moment the operands change on the next clock cycle — so it is captured into a register, which is sequential. The general pattern in every synchronous digital system is: combinational logic computes the next value, and sequential logic (a bank of flip-flops, clocked together) captures and holds that value until the next active clock edge, at which point the whole cycle repeats.
This register-combinational-register pattern is exactly what you will build formally once you reach registers (Module 9), counters (Module 10), and the CPU datapath (Module 15) — Module 7 and 8 exist to give you the storage primitive (the flip-flop) that every one of those later structures is assembled from.
Combinational vs. Sequential — quick-reference table
"Usually no clock" for combinational logic is not absolute — some combinational blocks are gated for power reasons, but that gating does not give them memory. A circuit can contain both kinds of logic; classify each block, not the whole chip, as one or the other.
Property | Combinational | Sequential
-----------|-----------------------|---------------------------
Output | f(current inputs) | f(inputs + current state)
Memory | No | Yes
Clock | Usually no | Often used
Feedback | None | Present
Examples | MUX, adder, decoder | Counter, register, latchCode Examples
For each row, apply the three-step test: the multiplexer, full adder, and decoder are pure forward trees of gates with no path routing an output back to an earlier stage — combinational. The latch has its own output wired directly back into a gate that helps produce that same output, and the counter's next state is computed from its own current stored state — both have feedback and are therefore sequential.
A wire that loops an output (or derived signal) back into the same circuit's input logic is the structural marker of sequential behavior.
Circuit | Feedback? | Classification
--------------------------|-----------|----------------
4-to-1 multiplexer | No | Combinational
Full adder | No | Combinational
Cross-coupled NOR latch | Yes | Sequential
3-bit binary counter | Yes | Sequential
7-segment decoder | No | CombinationalCombinational block vs. sequential block
The feedback arrow in the sequential diagram is the entire story: state loops back and is combined with new inputs on the next active clock edge.
Combinational:
inputs ---->[ AND / OR / NOT network ]----> output
(pure forward flow, no loop back)
Sequential:
____________________
inputs ------->| |------> output
clock ------->| logic + storage |
|____________________|
^ |
|________|
feedback (state)Important Rules
A circuit is sequential if and only if it contains a feedback path from an output (or internal storage node) back into its own input logic.
Combinational output depends only on present inputs; sequential output depends on present inputs AND stored state.
Storage elements (latches, flip-flops, registers, memories) are inherently sequential — any block instantiating one is sequential overall.
A clock pin strongly suggests sequential logic but is not proof by itself; asynchronous latches are sequential without being clocked.
The register-combinational-register pattern in every synchronous chip
Virtually every synchronous digital system — from a simple counter to a full CPU pipeline — is organized as alternating layers of combinational logic (computing a "next value") and sequential storage (a bank of flip-flops capturing that value on the clock edge, forming a clean boundary between pipeline stages). Static timing analysis tools in real chip design literally partition a netlist this way: they find every path that starts at one flip-flop's output, passes through only combinational logic, and ends at the next flip-flop's input, then check that the combinational delay along that path fits inside one clock period. Understanding the comb/seq boundary is therefore not just an academic classification exercise — it is the exact unit of analysis real-world timing closure is built around.
Assuming a circuit built entirely from ordinary logic gates (no dedicated flip-flop symbol) must be combinational.
Check for feedback loops explicitly — a handful of cross-coupled NAND or NOR gates with no separate "flip-flop" symbol on the schematic is still a sequential circuit (an SR latch) the moment an output wire is routed back into the gate network.
Sequential behavior is a structural property (feedback) not a component-library property. Two NOR gates wired output-to-input form a genuine memory cell even though nothing on the schematic is labeled "flip-flop".
A digital block has no explicit clock pin. Can it still be classified as sequential? A. No — sequential logic always requires a clock by definition B. Yes — an asynchronous latch is sequential (it has feedback and memory) despite being level-sensitive with no clock input C. No — only flip-flops count as sequential elements D. Yes, but only if it contains more than 10 gates
B. Yes — an asynchronous latch is sequential (it has feedback and memory) despite being level-sensitive with no clock input — Sequential means "has state via feedback," not "is clocked." A basic SR latch built from two cross-coupled gates has no clock pin at all, yet it is sequential because its output feeds back into its own input logic and it retains state.
Which pair correctly matches a combinational and a sequential example from the module's reference table? A. Combinational: counter, Sequential: adder B. Combinational: multiplexer, Sequential: register C. Combinational: register, Sequential: multiplexer D. Combinational: counter, Sequential: register
B. Combinational: multiplexer, Sequential: register — The multiplexer computes its output purely from current select/data inputs (no memory) and is combinational. A register explicitly stores a value across clock cycles, depending on its own prior state, and is sequential.
Classify each of the following as combinational or sequential, and justify each answer using the feedback test: (a) a binary-to-Gray-code converter, (b) a shift register, (c) a priority encoder, (d) a JK flip-flop.
(a) Combinational — pure XOR tree, output depends only on the current binary input. (b) Sequential — each stage's stored bit becomes the next stage's input on every clock edge, and the whole structure is built from flip-flops (feedback via clocked storage). (c) Combinational — priority resolution is a pure function of which inputs are currently asserted. (d) Sequential — a JK flip-flop's next output depends on both J/K and its own current Q (feedback), which is precisely why it can "toggle".
For each, ask: does any output (or an internal node derived from it) get routed back into the circuit's own input-side logic?