DAC Architectures, Output Stages & Reconstruction

Turning numbers back into analog signals. Learn DAC architectures (binary-weighted, R-2R ladder, string, current-steering, delta-sigma, PWM), voltage vs current outputs, output buffering, level shifting and scaling with op-amps, static specifications (offset, gain, INL, DNL, monotonicity), dynamic specifications (settling, glitch impulse, SFDR), zero-order-hold sinc droop and reconstruction filters, interpolation, and PWM-as-DAC filtering — with Python computing DAC outputs, sinc droop and INL/DNL from measured levels.

A DAC outputs a voltage or current proportional to a digital code. It drives audio outputs, waveform generators, control setpoints, bias trims and the reference paths inside SAR ADCs.

Its raw output is a staircase; analog circuitry scales, buffers and smooths it into the waveform you want.

An analogy

A DAC is like a set of precisely weighted coins: each bit adds its weight (½, ¼, ⅛ … of full scale) to the pile, and the total weight is the analog value. A reconstruction filter sands the staircase edges into a smooth ramp.

Architectures

Common DAC types:

Output conditioning

Voltage-output DACs may need buffering for loads and capacitive lines; current-output DACs use a TIA (op-amp with feedback resistor) or a resistor to convert to voltage. Op-amp circuits scale and offset the output (e.g. 0–2.5 V to ±10 V for industrial outputs), and must not limit settling or add noise. Watch the op-amp's slew rate, stability with cable capacitance, and the DAC's output impedance.

Reconstruction

A DAC's output is a series of held levels: its spectrum has images around multiples of f_s, shaped by sinc(f/f_s). A reconstruction (anti-imaging) filter removes images; digital interpolation (oversampling) pushes images to higher frequencies so a gentle analog filter suffices; a digital inverse-sinc pre-emphasis flattens the droop.

Dynamic effects

Major-carry transitions (0111… → 1000…) switch all bits and create glitches (glitch impulse, nV·s); deglitchers (track-and-hold) or segmented architectures reduce them. Settling time, output noise density, SFDR (especially for DDS and communications) and reference feedthrough determine AC performance.

Formulas

Worked example: LSB

Given: 10-bit, 3.3 V

Find: LSB.

Answer: 3.22 mV

Worked example: Droop at Nyquist

Given: f = f_s/2

Find: ZOH attenuation.

Answer: −3.92 dB

Worked example: Scaling to ±10 V

Given: DAC 0–2.5 V

Find: Gain and offset.

Answer: Gain 8, offset −10 V

R-2R ladder DAC with output buffer

  V_REF ─┬── 2R ── b3 switch (to V_REF or GND)
          R
          ├── 2R ── b2
          R
          ├── 2R ── b1
          R
          ├── 2R ── b0
          2R
          GND
  (MSB node) ──▷ buffer ── V_out = V_REF·code/2^N

Each ladder node sees 2R looking both ways, so current halves at every step — only two resistor values are needed, and matching (not absolute value) sets accuracy. A buffer amplifier provides low output impedance and optional gain/offset.

DAC levels, sinc droop and linearity

import math
# DAC: R-2R ladder output, reconstruction sinc droop, INL/DNL from measured levels
Vref, N = 2.5, 8
for code in (1, 128, 255):
    print(f"code {code:3d}: Vout = {Vref*code/2**N:.4f} V")
print(f"LSB = {Vref/2**N*1e3:.2f} mV")
fs = 48e3
for f in (1e3, 10e3, 20e3):
    x = math.pi * f / fs
    print(f"zero-order-hold droop at {f/1e3:4.0f} kHz: {20*math.log10(math.sin(x)/x):.2f} dB")
# 3-bit DAC measured levels (V) with 1 V LSB ideal
meas = [0.00, 1.05, 1.98, 3.10, 3.95, 5.02, 6.10, 6.98]
lsb = (meas[-1] - meas[0]) / 7                   # end-point fit
dnl = [((meas[i+1] - meas[i]) / lsb - 1) for i in range(7)]
inl = [((meas[i] - meas[0]) / lsb - i) for i in range(8)]
print("DNL (LSB):", [round(d, 2) for d in dnl])
print("INL (LSB):", [round(v, 2) for v in inl])
print(f"max |DNL| {max(abs(d) for d in dnl):.2f} LSB -> monotonic: {all(d > -1 for d in dnl)}")
# code   1: Vout = 0.0098 V
# code 128: Vout = 1.2500 V
# code 255: Vout = 2.4902 V
# LSB = 9.77 mV
# zero-order-hold droop at    1 kHz: -0.01 dB
# zero-order-hold droop at   10 kHz: -0.63 dB
# zero-order-hold droop at   20 kHz: -2.64 dB
# DNL (LSB): [0.05, -0.07, 0.12, -0.15, 0.07, 0.08, -0.12]
# INL (LSB): [0.0, 0.05, -0.01, 0.11, -0.04, 0.03, 0.12, 0.0]
# max |DNL| 0.15 LSB -> monotonic: True

An 8-bit, 2.5 V DAC has 9.77 mV steps and never reaches V_REF (max = V_REF − 1 LSB). The zero-order hold's sinc response costs 2.6 dB at 20 kHz with 48 kS/s — audio DACs oversample and compensate. The measured 3-bit DAC has |DNL| ≤ 0.15 LSB, so it is monotonic.

Common mistakes

Applications

Key takeaways

Going further