Analog Switches, Multiplexers & Switched-Capacitor Circuits

Routing and processing analog signals with switches. Learn MOSFET and CMOS transmission-gate switches, on-resistance and flatness, leakage, off-isolation and crosstalk, charge injection and clock feedthrough, multiplexers and settling in scanned systems, break-before-make, fault protection, sample-and-hold circuits, the switched-capacitor 'resistor' R = 1/(f·C), switched-capacitor integrators and filters set by capacitor ratios, and parasitic-insensitive topologies — with Python computing R_on errors, charge-injection steps, SC equivalent resistance and integrator frequency.

Analog switches let one ADC read many sensors, select gains and filters, sample signals and chop out offsets. Their imperfections — resistance that varies with voltage, injected charge, leakage — show up directly as measurement errors.

Switched-capacitor circuits turn capacitors and clocks into precise resistors and filters, the reason IC filters, delta-sigma ADCs and sample-and-holds are accurate without trimmed resistors.

An analogy

A switched capacitor is like a bucket brigade moving water between two tanks: each clock tick a small bucket (C) carries charge from one side to the other — the faster the ticks, the more flow, just like a smaller resistor.

Switch specifications

Key datasheet parameters:

Multiplexed acquisition

When a mux switches channels, the ADC input must settle from the previous channel's voltage to the new one through source resistance, R_on and filter capacitance — often the real speed limit. Add a buffer after the mux, keep source impedances low, or insert settling delays. Dummy conversions and channel ordering reduce crosstalk ('ghosting').

Sample-and-hold and charge injection

Turning off a MOS switch dumps part of its channel charge onto the hold capacitor (pedestal) and couples the clock through C_gd (feedthrough). Remedies: larger hold capacitors (slower), dummy switches, complementary switches, bottom-plate sampling and differential circuits that cancel common-mode injection. Hold-mode droop comes from leakage: dV/dt = I_leak/C_hold.

Switched-capacitor filters

Replacing integrator resistors with SC resistors gives integrators and biquads whose frequencies scale with the clock and depend on capacitor ratios (0.1% matching on chip). Parasitic-insensitive (stray-insensitive) integrators use two-phase non-overlapping clocks. SC circuits are sampled systems: they need anti-aliasing before them and smoothing after, and clock feedthrough appears as spurs at f_clk.

Formulas

Worked example: R_on error

Given: R_on 100 Ω into 1 kΩ

Find: Gain error.

Answer: 9.1% (use a buffer!)

Worked example: Charge injection

Given: 2 pC into 200 pF

Find: Step.

Answer: 10 mV

Worked example: SC resistor

Given: 1 pF at 50 kHz

Find: R_eq.

Answer: 20 MΩ

CMOS transmission gate and SC resistor

  Transmission gate:            Switched-capacitor resistor:
        φ                             φ1        φ2
   ─────┬──NMOS──┬─────          V1 ──/ ──┬── / ── V2
        └──PMOS──┘                         C
        φ̅                                 GND
  NMOS conducts near GND,          each clock cycle moves Q = C(V1 − V2)
  PMOS near V_DD → wide range      → average I = f·C·(V1 − V2) → R = 1/(fC)

Pairing NMOS and PMOS gives low resistance across the whole supply range. Toggling a capacitor between two nodes transfers a packet of charge each period — equivalent to a resistor whose value depends on clock frequency and capacitance, both precisely controlled in ICs.

Switch errors and switched-capacitor values

# Analog switches and switched capacitors: Ron error, charge injection, SC resistor and integrator
Ron, Rload = 50.0, 10e3
print(f"Ron 50 ohm into 10k: gain error {Ron/(Ron+Rload)*100:.2f}%; Ron flatness 5 ohm -> distortion-driving variation {5/(Ron+Rload)*100:.3f}%")
Qinj, Chold = 5e-12, 1e-9
print(f"charge injection 5 pC into 1 nF: {Qinj/Chold*1e3:.1f} mV step; into 100 pF: {Qinj/100e-12*1e3:.0f} mV")
fclk, Cs = 100e3, 10e-12
Req = 1 / (fclk * Cs)
print(f"switched capacitor 10 pF at 100 kHz behaves as R = {Req/1e6:.1f} Mohm")
C1, C2 = 1e-12, 10e-12
print(f"SC integrator unity-gain frequency = fclk*C1/(2*pi*C2) = {fclk*C1/(2*3.141592653589793*C2):.0f} Hz (set by a capacitor RATIO)")
Coff, Rsrc = 5e-12, 1e3
print(f"off-isolation at 1 MHz: Xc of 5 pF = {1/(2*3.141592653589793*1e6*Coff)/1e3:.1f} kohm")
# Ron 50 ohm into 10k: gain error 0.50%; Ron flatness 5 ohm -> distortion-driving variation 0.050%
# charge injection 5 pC into 1 nF: 5.0 mV step; into 100 pF: 50 mV
# switched capacitor 10 pF at 100 kHz behaves as R = 1.0 Mohm
# SC integrator unity-gain frequency = fclk*C1/(2*pi*C2) = 1592 Hz (set by a capacitor RATIO)
# off-isolation at 1 MHz: Xc of 5 pF = 31.8 kohm

50 Ω of R_on into 10 kΩ costs 0.5% gain error, and its variation with signal voltage causes distortion. 5 pC of injected charge makes a 50 mV step on a 100 pF hold capacitor — choose bigger hold caps or low-Q_inj switches. A 10 pF capacitor clocked at 100 kHz acts like 1 MΩ; an SC integrator's frequency depends only on a capacitor ratio and the clock.

Common mistakes

Applications

Key takeaways

Going further