Sampling, Sample-and-Hold & ADC Front-End Design

Connecting the analog world to an ADC without losing accuracy. Learn sampling and the Nyquist theorem, aliasing and anti-aliasing filters, sample-and-hold operation (acquisition, aperture, droop, pedestal), ADC architectures (SAR, delta-sigma, pipeline, flash) and their input structures, switched-capacitor input kickback, driver amplifier and RC 'charge-bucket' filter design, settling to N bits, single-ended vs differential inputs, input range and common mode, aperture jitter limits, and ADC specifications (offset, gain, INL, DNL, SNR, SINAD, ENOB, SFDR) — with Python computing alias frequencies, settling time constants, kickback RC and jitter-limited SNR.

An ADC measures a voltage at discrete instants. Whatever reaches its input at the sampling moment — signal, noise, out-of-band interference, settling error — becomes the digital number. The front end decides whether the ADC achieves its datasheet performance.

Two key ideas: frequencies above half the sample rate fold back into the band (aliasing), and the ADC's sampling capacitor must be charged to within a fraction of an LSB in the available acquisition time.

An analogy

Sampling is like filming a spinning wheel: if the camera's frame rate is too slow, the wheel appears to turn slowly backwards (aliasing). The front-end filter makes sure nothing spins faster than the camera can capture.

Sampling and aliasing

Sampling multiplies the spectrum into copies around every multiple of f_s. Any content above f_s/2 folds into the 0–f_s/2 band, indistinguishable from real signals. Anti-aliasing filters must attenuate everything that could alias into the band of interest below the required noise floor. Oversampling (f_s ≫ 2f_max) relaxes the analog filter; digital decimation filters finish the job — the delta-sigma approach.

ADC architectures

Choose by speed and resolution:

Driving the ADC

Choose a driver with enough bandwidth to settle, low noise and distortion better than the ADC, and output swing covering the ADC range. Use differential drivers for differential ADCs (better SNR and even-order cancellation), set the common-mode to V_REF/2, and match the RC filter's time constant to acquisition time. Include the driver noise over the RC filter bandwidth in the SNR budget. Keep the reference pin decoupled and the analog/digital grounds correctly joined under the ADC.

Specifications

Static: offset, gain error, INL (deviation from a straight line), DNL (step-size error; < −1 LSB means missing codes). Dynamic: SNR, THD, SINAD → ENOB, SFDR, full-power bandwidth, aperture delay and jitter. Test with a coherent, very clean sine and an FFT; histogram tests reveal DNL/INL.

Formulas

Worked example: Alias

Given: 45 kHz tone, f_s = 40 kS/s

Find: Apparent frequency.

Answer: 5 kHz

Worked example: Jitter

Given: 1 ps rms, 50 MHz input

Find: SNR limit.

Answer: ≈ 70 dB

Worked example: Settling for 12 bits

Given: N = 12

Find: Time constants.

Answer: ≈ 9.0 τ

SAR ADC driver with charge-bucket filter

  signal ── anti-alias ──▷ driver op-amp ── R 20 Ω ──┬── ADC IN (switch + C_S 30 pF)
             filter        (fast, low-noise,             C 2.7 nF (C0G)
                            low output Z)               GND
  During acquisition C_S connects: the 2.7 nF 'bucket' supplies the charge instantly,
  then the op-amp recharges it through R before the conversion starts.

The ADC's switched sampling capacitor draws a burst of charge (kickback). A large C0G capacitor next to the pin supplies it with only a ~1% dip, and the series resistor isolates the op-amp from this capacitive load (stability) while forming a noise-limiting filter. R·C must still settle within the acquisition time.

Aliasing, settling and jitter

import math
# Sampling: aliasing, SAR input settling, kickback RC, aperture jitter limit
fs = 100e3
for f in (30e3, 70e3, 130e3, 190e3):
    alias = abs(f - fs * round(f / fs))
    print(f"input {f/1e3:5.0f} kHz sampled at 100 kS/s appears at {alias/1e3:4.0f} kHz")
N = 16
tau_n = math.log(2 ** (N + 1))
print(f"{N}-bit settling to 1/2 LSB needs {tau_n:.1f} time constants")
t_acq = 1.5e-6                                   # acquisition time
R, C = 20.0, 2.7e-9                              # kickback RC filter
print(f"RC = {R*C*1e9:.0f} ns -> {t_acq/(R*C):.1f} tau in {t_acq*1e6:.1f} us ({'OK' if t_acq/(R*C) > tau_n else 'too slow'})")
print(f"RC filter corner {1/(2*math.pi*R*C)/1e6:.2f} MHz; charge sharing: Csample 30 pF vs Cfilter 2.7 nF -> dip {30e-12/(30e-12+2.7e-9)*100:.1f}% of step")
for tj in (1e-12, 10e-12, 100e-12):
    print(f"jitter {tj*1e12:5.0f} ps at 10 MHz input: SNR limit {-20*math.log10(2*math.pi*10e6*tj):.1f} dB")
# input    30 kHz sampled at 100 kS/s appears at   30 kHz
# input    70 kHz sampled at 100 kS/s appears at   30 kHz
# input   130 kHz sampled at 100 kS/s appears at   30 kHz
# input   190 kHz sampled at 100 kS/s appears at   10 kHz
# 16-bit settling to 1/2 LSB needs 11.8 time constants
# RC = 54 ns -> 27.8 tau in 1.5 us (OK)
# RC filter corner 2.95 MHz; charge sharing: Csample 30 pF vs Cfilter 2.7 nF -> dip 1.1% of step
# jitter     1 ps at 10 MHz input: SNR limit 84.0 dB
# jitter    10 ps at 10 MHz input: SNR limit 64.0 dB
# jitter   100 ps at 10 MHz input: SNR limit 44.0 dB

At 100 kS/s, 30, 70 and 130 kHz inputs all land at 30 kHz — indistinguishable after sampling, so they must be filtered out before the ADC. A 16-bit SAR needs 11.8 time constants of settling; a 54 ns RC gives 28 τ in 1.5 µs. Clock jitter matters for high input frequencies: 10 ps limits SNR at 10 MHz to 64 dB — barely 10.3 bits.

Common mistakes

Applications

Key takeaways

Going further