Intermediate Electronics / VLSI interview questions

150 questions with answers (VLS-151 to VLS-300). Try each one aloud before reading the answer.

MOSFET Device Physics

VLS-151 · What is the long-channel saturation current equation for an NMOS?

ID = ½·μn·Cox·(W/L)·(VGS − Vt)²·(1 + λ·VDS). Current rises with the square of the gate overdrive, with mobility, oxide capacitance and W/L.

VLS-152 · What is the drain current equation in the linear region?

ID = μn·Cox·(W/L)·[(VGS − Vt)·VDS − VDS²/2]. For small VDS the device acts as a resistor with R ≈ 1 / [μn·Cox·(W/L)·(VGS − Vt)].

VLS-153 · Why does a PMOS need a larger width than an NMOS?

Hole mobility is about 2–3 times lower than electron mobility, so a PMOS of the same size has less drive current. Making it 2–3 times wider balances the rise and fall times.

VLS-154 · What are short-channel effects?

Effects that appear when channel length is comparable to the depletion widths: threshold voltage roll-off, drain-induced barrier lowering, velocity saturation, mobility degradation and increased leakage. The drain begins to control the channel along with the gate.

VLS-155 · What is DIBL?

Drain-induced barrier lowering: in short channels a high drain voltage lowers the source-channel potential barrier, reducing Vt and increasing off-current. It is quoted in mV/V.

VLS-156 · How does velocity saturation change the current equation?

At high lateral fields carrier velocity saturates near 10⁷ cm/s in silicon, so saturation current becomes roughly linear in (VGS − Vt) instead of square-law: IDsat ≈ W·Cox·vsat·(VGS − Vt).

VLS-157 · How does temperature affect MOSFET drive current?

Higher temperature reduces carrier mobility, which lowers current, and also reduces Vt, which raises current. At high overdrive mobility dominates and devices slow down; at low supply the Vt effect can dominate.

VLS-158 · What is subthreshold swing, and what is its limit?

The gate voltage change needed to change subthreshold current by 10×: S = (kT/q)·ln10·(1 + Cd/Cox). Its ideal limit is about 60 mV/decade at 300 K; real devices are higher.

VLS-159 · What is GIDL?

Gate-induced drain leakage: a strong field in the gate-drain overlap region, when the gate is off and the drain is high, causes band-to-band tunnelling current to the body. It worsens with thin oxides and high drain bias.

VLS-160 · How does body bias change the threshold voltage?

Vt = Vt0 + γ·(√(2φF + VSB) − √(2φF)), where γ is the body-effect coefficient and φF the Fermi potential. Reverse body bias raises Vt and forward body bias lowers it.

VLS-161 · What is the transconductance of a MOSFET in saturation?

gm = ∂ID/∂VGS = μn·Cox·(W/L)·(VGS − Vt) = 2·ID/(VGS − Vt). It measures how strongly the gate voltage controls the drain current.

VLS-162 · What is equivalent oxide thickness (EOT)?

The SiO₂ thickness that would give the same capacitance as a high-k layer: EOT = tHK·(3.9/kHK). A high-k film can be physically thicker, cutting tunnelling, while keeping a small EOT.

VLS-163 · What is hot-carrier injection?

High-energy carriers near the drain gain enough energy to be injected into the gate oxide, where they are trapped. This shifts Vt and degrades mobility over time, slowing the device.

CMOS Logic & Circuit Design

VLS-164 · How do you size a 2-input NAND for the same drive as a unit inverter?

If the inverter is NMOS W = 1, PMOS W = 2, the NAND uses NMOS W = 2 each (two in series) and PMOS W = 2 each (parallel, only one needs to pull up). Input capacitance is 4 versus 3 for the inverter.

VLS-165 · What is logical effort?

The ratio of a gate's input capacitance to that of an inverter delivering the same output current. With a PMOS/NMOS ratio of 2, the inverter has g = 1, NAND2 has g = 4/3 and NOR2 has g = 5/3.

VLS-166 · What is the delay equation in the logical effort model?

d = g·h + p, in units of τ, where g is logical effort, h = Cout/Cin is electrical effort, and p is parasitic delay (about 1 for an inverter, 2 for NAND2).

VLS-167 · How does the β ratio affect the inverter switching threshold?

Increasing PMOS strength relative to NMOS (larger βp/βn) shifts VM toward VDD; a stronger NMOS shifts it toward ground. Skewed inverters use this to speed up one transition.

VLS-168 · When does short-circuit power occur?

During an input transition when Vtn < Vin < VDD − |Vtp|, both NMOS and PMOS conduct briefly, so current flows from VDD to ground. It grows with slow input slew, so slews are kept sharp.

VLS-169 · How does dynamic (domino) logic work?

In the precharge phase (clock low) a PMOS charges the dynamic node high. In the evaluate phase (clock high) an NMOS network may discharge it. A static inverter after the node makes outputs monotonic for cascading.

VLS-170 · What is charge sharing in dynamic logic?

During evaluation, charge on the precharged node redistributes to discharged internal nodes of the NMOS stack even if no path to ground exists, lowering the output voltage. Keepers and precharging internal nodes reduce it.

VLS-171 · Why does an NMOS pass a weak 1?

As the output rises it reaches VDD − Vt, where VGS of the NMOS falls to Vt and it turns off. A PMOS similarly passes a weak 0, which is why transmission gates use both.

VLS-172 · What is latch-up, and how is it prevented?

A parasitic PNPN thyristor formed by the n-well and substrate turns on and shorts VDD to ground, possibly destroying the chip. It is prevented with well and substrate taps, guard rings, adequate spacing and SOI.

VLS-173 · Why drive a large load with a tapered inverter chain?

One small gate driving a large capacitance is slow. A chain of inverters each larger by a fixed factor minimizes total delay; the optimal stage effort is about 4 (about e when parasitics are ignored).

VLS-174 · What is Elmore delay?

An RC tree delay estimate: the sum over each resistor on the path of its resistance times all downstream capacitance it charges, τ = Σ Rᵢ·C(downstream of i). It is an upper bound on the 50% delay.

VLS-175 · What is the stack effect?

Two or more series off-transistors leak much less than one, because the intermediate node rises, which makes VGS negative and adds body effect on the upper device. It is used for leakage reduction.

VLS-176 · How does a 6T SRAM cell work?

Two cross-coupled inverters store a bit, and two NMOS access transistors connect the nodes to the bit lines when the word line is high. Reads sense a small differential on precharged bit lines; writes overpower the cell through the bit lines.

Digital Design Fundamentals

VLS-177 · What are setup time and hold time?

Setup time is the minimum time data must be stable before the active clock edge. Hold time is the minimum time it must stay stable after the edge. Violating either can cause wrong capture or metastability.

VLS-178 · What is clock-to-Q delay?

The time from the active clock edge to the flip-flop output changing (tcq). It is part of every register-to-register path delay.

VLS-179 · What is the setup constraint for a register-to-register path?

Tclk ≥ tcq + tcomb,max + tsetup − tskew, where tskew = capture clock arrival − launch clock arrival. Maximum frequency is 1/Tclk,min.

VLS-180 · What is the hold constraint for a register-to-register path?

tcq + tcomb,min ≥ thold + tskew. It does not include the clock period, so hold must be fixed by adding delay or reducing skew, not by changing frequency.

VLS-181 · What is a static hazard, and how is it removed?

A momentary glitch on an output that should stay constant, caused by unequal path delays. A static-1 hazard in SOP logic is removed by adding the redundant consensus term covering adjacent K-map groups.

VLS-182 · Why is a carry-lookahead adder faster than a ripple-carry adder?

A ripple adder waits for each carry in turn, so delay grows as O(N). Lookahead computes carries in parallel from generate Gᵢ = AᵢBᵢ and propagate Pᵢ = Aᵢ ⊕ Bᵢ, and tree versions reach O(log N).

VLS-183 · How do you build a divide-by-2 clock with a D flip-flop?

Feed the inverted output Q' back to D. The flop toggles every rising edge, so Q has half the input frequency with a 50% duty cycle.

VLS-184 · How do you convert binary to Gray code and back?

Binary to Gray: g = b ^ (b >> 1). Gray to binary: b[MSB] = g[MSB] and b[i] = b[i+1] ^ g[i], working from MSB to LSB.

VLS-185 · How many 2-input NAND gates make an XOR?

Four. With n1 = NAND(A,B), the output is NAND(NAND(A,n1), NAND(B,n1)).

VLS-186 · How do you implement any function of n variables with a mux?

Use a 2ⁿ:1 mux with the variables on the selects and constants on the data inputs. Or use a 2ⁿ⁻¹:1 mux with n−1 variables on the selects and the last variable, its complement, 0 or 1 on the data inputs.

VLS-187 · How do ring and Johnson counters differ?

A ring counter circulates a single 1 and has N states with N flops. A Johnson (twisted-ring) counter feeds back the inverted last output and has 2N states with N flops.

VLS-188 · How is overflow detected in two's complement addition?

Overflow occurs when two operands of the same sign give a result of the opposite sign. Equivalently, overflow = carry into the MSB ⊕ carry out of the MSB.

VLS-189 · What is a Wallace tree multiplier?

A multiplier that reduces partial products in parallel using layers of full and half adders (carry-save adders) until two rows remain, which a fast adder then sums. Reduction depth grows as O(log N).

Verilog & SystemVerilog

VLS-190 · What is the difference between blocking and non-blocking assignments?

Blocking (=) executes immediately and in order, so later statements see the new value; use it for combinational logic. Non-blocking (<=) evaluates the right side now and updates at the end of the time step; use it for sequential logic.

VLS-191 · What are the main Verilog scheduling regions?

Within one time step: active (blocking assignments, continuous assignments, evaluating RHS of NBAs), inactive (#0), NBA update, then monitor/postponed ($monitor, $strobe). SystemVerilog adds observed, reactive and other regions for assertions and programs.

VLS-192 · What is the difference between a task and a function?

A function returns a value (or is void), runs in zero simulation time, and cannot contain delays or event controls. A task can have multiple outputs and can consume time with delays or waits.

VLS-193 · What is the difference between case, casez and casex?

case matches x and z literally. casez treats z (or ?) as don't-care. casex treats both x and z as don't-care, which can hide x bugs, so casez or case inside is preferred.

VLS-194 · What is the difference between $display, $monitor and $strobe?

$display prints immediately when executed. $strobe prints at the end of the time step, after non-blocking updates. $monitor prints whenever any of its arguments changes.

VLS-195 · Write a D flip-flop with asynchronous active-low reset.

always_ff @(posedge clk or negedge rst_n)
  if (!rst_n) q <= 1'b0;
  else        q <= d;

The reset appears in the sensitivity list, so it acts without waiting for the clock.

VLS-196 · What are SystemVerilog interfaces and modports?

An interface bundles related signals (and optionally tasks and assertions) into one port. Modports define direction views, such as master and slave, for each module that connects to it.

VLS-197 · What is the difference between packed and unpacked arrays?

Packed dimensions (before the name, logic [7:0] a) form a contiguous bit vector usable in arithmetic. Unpacked dimensions (after the name, logic a [8]) form an array of separate elements, like memory.

VLS-198 · What are dynamic arrays, associative arrays and queues?

A dynamic array is sized at runtime with new[]. An associative array is indexed by any key type and stores only written entries. A queue ([$]) is a resizable ordered list with push and pop methods.

VLS-199 · What is the difference between fork-join, join_any and join_none?

join waits for all forked threads to finish, join_any continues when any one finishes, and join_none continues immediately, leaving the threads running in the background.

VLS-200 · What is a race condition in Verilog, and how do clocking blocks help?

A race occurs when the result depends on the order in which the simulator executes processes at the same time step, such as a testbench driving a signal at the clock edge. Clocking blocks sample inputs and drive outputs with defined skew, removing that ambiguity.

VLS-201 · What is a virtual interface?

A class-side handle to a static interface instance. It lets dynamic UVM objects such as drivers and monitors access DUT signals; it is usually passed through uvm_config_db.

VLS-202 · What happens when signed and unsigned operands are mixed in an expression?

If any operand is unsigned, the whole expression is evaluated as unsigned, so negative values become large positive numbers. Use $signed() casts or declare all operands signed.

RTL Design, FSMs & CDC

VLS-203 · What is the recommended RTL style for an FSM?

Use a sequential block for the state register and a combinational block for next-state and outputs, with a default assignment to avoid latches:

always_ff @(posedge clk or negedge rst_n)
  if (!rst_n) state <= IDLE; else state <= next;
always_comb begin
  next = state;
  case (state) IDLE: if (go) next = RUN; RUN: if (done) next = IDLE; endcase
end

VLS-204 · When is one-hot encoding preferred over binary?

When flops are cheap and speed matters, as in FPGAs: next-state logic is simple and shallow, and state decoding needs one bit. Binary suits large FSMs in area-sensitive ASICs.

VLS-205 · How many states does an overlapping "1011" sequence detector need?

Four states for a Mealy machine (S0, S1, S10, S101), with the output asserted on the transition when the final 1 arrives. A Moore machine needs five, adding a state for "1011" detected.

VLS-206 · Why does a synchronizer use two flip-flops?

The first flop may go metastable when it samples an asynchronous input. A full destination clock period lets it resolve before the second flop samples it, so the probability of passing metastability on drops exponentially. More flops are used at very high frequencies.

VLS-207 · Why are async FIFO pointers Gray-coded before synchronizing?

Only one bit changes per increment, so if the synchronizer samples during a change the received value is either the old or the new pointer, never an invalid mix. A binary pointer could change many bits at once and be misread.

VLS-208 · How do you pass a single-cycle pulse from a fast to a slow clock domain?

A pulse shorter than the slow period can be missed. Convert it to a level by toggling a flop in the source domain, synchronize the toggle with two flops, and recover a pulse with an XOR edge detector in the destination domain. A handshake also works.

VLS-209 · Why can't you synchronize each bit of a multi-bit bus separately?

Bits can resolve on different destination cycles because of skew and metastability, so the receiver may see an incoherent mix of old and new values. Use a handshake with a qualifying enable, an async FIFO, or Gray code for counters.

VLS-210 · Write a reset synchronizer.

always_ff @(posedge clk or negedge arst_n)
  if (!arst_n) {rst_n, r1} <= 2'b00;
  else         {rst_n, r1} <= {r1, 1'b1};

Reset asserts asynchronously and releases two clocks later, synchronized to clk.

VLS-211 · How does pipelining affect latency and throughput?

Throughput rises to about one result per (shorter) clock cycle, but latency in time rises slightly because of register overhead (tcq + tsetup per stage). An N-stage pipeline has N cycles of latency.

VLS-212 · What is reconvergence in CDC?

Two or more signals that are synchronized separately and then recombine in the destination domain. Because each may resolve on a different cycle, the combined logic can see illegal combinations.

VLS-213 · How do you build a glitch-free clock multiplexer?

Use cross-coupled enable logic in which each clock's enable flop, clocked on the falling edge of its own clock, is gated by the other's disabled state. The current clock stops while low before the new clock starts while low, so no runt pulse occurs.

VLS-214 · How do you avoid inferring latches in combinational blocks?

Assign default values to every output at the top of the block, cover every branch with else and default, and use always_comb so tools warn about latch inference.

VLS-215 · How do you write a rising-edge detector for a synchronous signal?

Register the signal and AND the current value with the inverted delayed value:

always_ff @(posedge clk) d_q <= d;
assign rise = d & ~d_q;

For an asynchronous input, synchronize it first.

Functional Verification (UVM, Assertions, Coverage)

VLS-216 · What are the main UVM phases?

Build, connect, end_of_elaboration and start_of_simulation (function phases), then run (task phase, with sub-phases such as reset, configure, main, shutdown), followed by extract, check, report and final. Build runs top-down; the others mostly run bottom-up.

VLS-217 · What is the UVM factory?

A mechanism for creating objects and components through type_id::create() instead of new(), so tests can override types or instances, for example replacing a driver with an error-injecting one, without editing the environment.

VLS-218 · What is uvm_config_db used for?

Passing configuration objects, virtual interfaces and settings down the component hierarchy by path and field name with set() and get(), without hard-coded connections.

VLS-219 · What is a virtual sequence?

A sequence that coordinates several sub-sequences on different agents' sequencers, usually through a virtual sequencer holding their handles, to create system-level scenarios.

VLS-220 · What are TLM analysis ports in UVM?

Broadcast ports through which a component such as a monitor calls write() to send transactions to any number of subscribers, such as scoreboards and coverage collectors. They are non-blocking and work even with no subscribers.

VLS-221 · What is the objection mechanism in UVM?

Components raise objections to keep a run-time phase active and drop them when finished. The phase ends when all objections are dropped, which decides when simulation stops.

VLS-222 · What is the difference between |-> and |=> in SVA?

|-> is overlapping implication: the consequent is checked in the same cycle as the antecedent's match. |=> is non-overlapping: it is checked one cycle later, equivalent to |-> ##1.

VLS-223 · Write an assertion that ack follows req within 1 to 3 cycles.

assert property (@(posedge clk) disable iff (!rst_n)
  req |-> ##[1:3] ack);

It fails if ack is not high in any of the three cycles after req.

VLS-224 · What is cross coverage?

Coverage of combinations of two or more coverpoints, for example every packet type with every length bin. It reveals untested interactions that individual coverpoints miss.

VLS-225 · How do dist and solve...before work in constraints?

dist weights the random distribution, for example len dist {[1:4]:/80, [5:64]:/20};. solve a before b changes the probability distribution by choosing a first, without changing the legal solution set.

VLS-226 · What are illegal_bins and ignore_bins?

ignore_bins excludes values from coverage calculation. illegal_bins also excludes them but reports an error if they are ever sampled, acting as a checker.

VLS-227 · What is formal property checking?

A tool proves that assertions hold for all reachable states and legal inputs (under assumptions), or produces a counterexample trace. A bounded proof only guarantees correctness up to a given number of cycles.

VLS-228 · What is the difference between active and passive UVM agents?

An active agent has a sequencer, driver and monitor and drives stimulus into the DUT. A passive agent has only a monitor and observes an interface, for example an internal bus or DUT output.

Static Timing Analysis

VLS-229 · Calculate the setup slack: Tclk = 2 ns, tcq = 0.2 ns, logic = 1.4 ns, tsetup = 0.1 ns, zero skew.

Arrival = 0.2 + 1.4 = 1.6 ns. Required = 2.0 − 0.1 = 1.9 ns. Setup slack = 1.9 − 1.6 = +0.3 ns, so the path meets timing.

VLS-230 · Calculate the hold slack: tcq = 0.1 ns, min logic = 0.05 ns, thold = 0.08 ns, skew = +0.1 ns.

Arrival = 0.1 + 0.05 = 0.15 ns. Required = thold + skew = 0.08 + 0.1 = 0.18 ns. Hold slack = 0.15 − 0.18 = −0.03 ns, a violation that needs about 30 ps of added delay.

VLS-231 · What is clock skew, and how do positive and negative skew affect timing?

Skew is the difference in clock arrival times at two flops. With skew = capture − launch, positive skew helps setup but hurts hold; negative skew hurts setup but helps hold.

VLS-232 · What is on-chip variation (OCV) derating?

Applying derate factors so that, for setup, launch clock and data paths are made slower and the capture clock faster (and the reverse for hold). This models local process, voltage and temperature variation across the die.

VLS-233 · What is CRPR (or CPPR)?

Clock reconvergence (common path) pessimism removal. OCV gives the shared part of the launch and capture clock paths both early and late delays at once, which is impossible, so the tool adds that difference back as credit.

VLS-234 · What is the difference between NLDM and CCS models?

NLDM gives cell delay and output slew as tables indexed by input slew and load capacitance, assuming a voltage source driver. CCS models the output current waveform, so it is more accurate for resistive loads and at advanced nodes.

VLS-235 · What do set_input_delay and set_output_delay specify?

The time external logic uses relative to a clock: input delay is when data arrives at an input port after the launch edge; output delay is how much of the cycle the external capture path needs. They constrain I/O paths.

VLS-236 · What is a generated clock?

A clock derived from a master clock inside the design, for example by a divider or clock mux. create_generated_clock tells STA its source, ratio and phase so its latency is traced from the master.

VLS-237 · What are recovery and removal checks?

Timing checks on asynchronous set and reset deassertion relative to the clock. Recovery is like setup (release must happen early enough before the edge); removal is like hold (release must not happen too soon after the edge).

VLS-238 · What is time borrowing in latch-based design?

Because a latch is transparent while its enable is active, data arriving late can pass through and use time from the next stage. STA lets a path borrow up to the transparency window minus setup.

VLS-239 · What are max transition, max capacitance and max fanout?

Design rule constraints (DRVs). They limit slew on any net, load capacitance a driver sees, and the number of loads, keeping cells within the characterized ranges of their tables and limiting power and noise.

VLS-240 · What is the difference between GBA and PBA?

Graph-based analysis uses the worst slew at each node for all paths through it, which is fast but pessimistic. Path-based analysis recomputes each path with its actual slews, which is more accurate and slower, and is used to remove false violations.

Logic Synthesis

VLS-241 · What are the main steps of a synthesis flow?

Read RTL and libraries, elaborate, apply constraints, compile (generic optimization, technology mapping, timing, area and power optimization), insert scan if required, then write out the netlist, SDC and reports.

VLS-242 · How does synthesis decide between a flip-flop and a latch?

Edge-triggered event control (posedge/negedge) infers flip-flops. A level-sensitive block where a variable is not assigned on every path infers a latch. Fully assigned combinational blocks infer only gates.

VLS-243 · What is resource sharing?

Using one operator, such as an adder or multiplier, for several mutually exclusive operations, with muxes selecting the operands. It saves area but adds mux delay.

VLS-244 · What is retiming?

Moving registers across combinational logic without changing cycle-level I/O behaviour, to balance stage delays and improve frequency. It can change the number of registers and makes equivalence checking harder.

VLS-245 · Why does synthesis duplicate registers?

A high-fanout register drives a large load and slows paths. Duplicating it splits the load so each copy drives fewer cells, which improves timing at the cost of area.

VLS-246 · What are ungrouping and boundary optimization?

Ungrouping dissolves a module's hierarchy into its parent so logic can be optimized together. Boundary optimization propagates constants and removes unused ports across hierarchy boundaries while keeping the hierarchy.

VLS-247 · How does physical-aware synthesis differ from wire-load-based synthesis?

It uses floorplan data and fast placement to estimate real wire lengths and parasitics, instead of statistical wire-load models. This gives better correlation with place-and-route timing.

VLS-248 · Why is LEC run after synthesis?

Synthesis optimizations or tool bugs could change function. LEC maps compare points (registers, ports, black boxes) between RTL and netlist and formally proves that their logic cones are equivalent.

VLS-249 · How does synthesis insert clock gating?

It finds registers that load under a common enable (if (en) q <= d;) and replaces the feedback mux with an ICG cell on their clock. A minimum bit-width threshold is usually set so small groups are not gated.

VLS-250 · What is multi-bit flip-flop banking?

Merging several single-bit flops that share clock and control into one multi-bit cell. This reduces area, clock pin capacitance and clock tree power.

VLS-251 · How are max fanout and transition violations fixed in synthesis?

By buffering (building buffer trees), upsizing drivers, cloning drivers and restructuring logic, guided by library DRV limits and SDC constraints.

VLS-252 · What does constant propagation do in synthesis?

It replaces logic driven by constants with simpler logic, and removes registers with constant values or no loads. It can remove intended logic if constraints or ties are wrong.

Physical Design (Floorplan, Placement, CTS, Routing, Signoff)

VLS-253 · Find the core area for 0.6 mm² of cells at 70% utilization with aspect ratio 1.

Core area = 0.6 / 0.7 ≈ 0.857 mm². Side = √0.857 ≈ 0.926 mm, so the core is about 0.93 mm × 0.93 mm, before adding I/O ring area.

VLS-254 · What are good practices for macro placement?

Place macros near the core edges with pins facing the core, group by connectivity and data flow, leave channels for routing and power, add halos and blockages, and avoid macros that block cell rows near I/O.

VLS-255 · How is a power grid planned?

Choose ring and strap widths, pitch and layers so that IR drop and electromigration meet limits for the estimated current. Rails run on the lowest metal along cell rows, connected to upper-metal straps with via stacks.

VLS-256 · What are the stages of placement?

Global placement spreads cells to minimize wirelength and congestion, legalization snaps them to rows and sites without overlap, and detailed placement refines locally. Timing-driven optimization runs throughout.

VLS-257 · How is routing congestion measured?

By overflow: the routing demand of g-cells compared with available tracks per layer, shown as congestion maps. Overflow above zero in many g-cells means detailed routing may fail or detour.

VLS-258 · What are the main targets of CTS?

Low skew, controlled insertion delay (latency), maximum transition and capacitance on clock nets, minimal power and area, and robustness to variation.

VLS-259 · What are common clock distribution topologies?

H-tree (symmetric, low skew), clock mesh (very low skew and variation tolerance, high power), spine or fishbone structures, and conventional buffered trees built by CTS tools. Many designs combine them.

VLS-260 · Why are non-default routing rules (NDR) used for clock nets?

Wider wires lower resistance and electromigration risk, and double spacing lowers coupling capacitance and crosstalk. Shielding may also be used. This keeps clock slew and skew predictable.

VLS-261 · What are crosstalk delay and crosstalk noise?

Coupling capacitance between adjacent nets lets an aggressor's transition change a victim's delay (speed up or slow down) or inject a glitch onto a quiet victim. Both can cause timing or functional failures.

VLS-262 · What is the antenna effect, and how is it fixed?

During fabrication, long metal connected only to a gate collects plasma charge that can damage the gate oxide. Fixes include layer jumping to a higher metal, antenna diodes and breaking long wires.

VLS-263 · What is electromigration?

Gradual movement of metal atoms caused by high current density, leading to voids (opens) or hillocks (shorts) over time. It is managed with current density limits, wider wires and more vias.

VLS-264 · What are filler, decap, tap and endcap cells?

Filler cells close gaps in rows for well and implant continuity. Decaps add local supply capacitance. Tap cells connect wells and substrate to supplies to prevent latch-up. Endcaps terminate rows at the edges.

Low-Power Design

VLS-265 · What is the dynamic power formula, and which term gives the biggest saving?

P = α·C·V²·f, where α is activity, C is switched capacitance, V is supply and f is frequency. Supply voltage gives the biggest saving because power scales with V².

VLS-266 · How much dynamic power is saved by lowering VDD from 1.0 V to 0.8 V at the same frequency?

Power scales with V², so the ratio is 0.8² = 0.64. That is a 36% saving. Frequency usually also drops, adding further savings.

VLS-267 · What are the main leakage components?

Subthreshold leakage (usually dominant), gate-oxide tunnelling leakage, junction reverse-bias leakage, and GIDL. Subthreshold leakage rises exponentially as Vt falls and as temperature rises.

VLS-268 · Why is an ICG cell built with a latch?

A latch transparent while the clock is low holds the enable stable during the clock's high phase. The AND output therefore cannot glitch when the enable changes mid-cycle. A plain AND gate could produce clock glitches.

VLS-269 · What is in-rush current in power gating?

The large current that flows when switches turn on and charge the gated domain's capacitance. It can cause IR drop in neighbouring domains, so switches are turned on gradually, for example in daisy chains.

VLS-270 · Where are isolation cells placed, and what values do they clamp?

Usually on outputs of a switchable domain, powered from the always-on supply, often physically placed in the receiving domain. They clamp to 0, 1 or the latched last value, chosen so the receiving logic stays in a safe state.

VLS-271 · What types of level shifter are used?

Low-to-high shifters, often cross-coupled differential cells needing both supplies, and high-to-low shifters, which can be simple buffers. Enable level shifters combine shifting with isolation for power-gated sources.

VLS-272 · What is operand isolation?

Holding the inputs of a datapath unit such as a multiplier constant (with AND gates or latches) when its output is not used, so it does not switch unnecessarily.

VLS-273 · How are multi-Vt cells used in a design?

Start with high- or standard-Vt cells for low leakage and swap low-Vt cells only onto critical paths that miss timing. The leakage-recovery step then swaps cells on paths with positive slack back to high Vt.

VLS-274 · Which UPF commands describe a power-gated domain?

create_power_domain, create_supply_net and create_supply_port, create_power_switch, set_isolation with set_isolation_control, set_retention with its controls, set_level_shifter, and add_power_state for power modes.

VLS-275 · What is body biasing?

Changing the body voltage to tune threshold voltage after fabrication. Reverse body bias raises Vt and cuts leakage in standby; forward body bias lowers Vt and boosts speed. It is most effective on FD-SOI.

VLS-276 · What is glitch power, and how is it reduced?

Power wasted by spurious transitions caused by unequal path delays, common in arithmetic logic. It is reduced by balancing paths, pipelining, retiming and operand isolation.

Design for Testability

VLS-277 · How is scan inserted into a design?

Synthesis replaces each flop with a scan flop, then stitches scan-out to scan-in to form chains with scan-in and scan-out ports and a scan-enable signal, following DFT rules and chain-length targets.

VLS-278 · What is the sequence of one scan test pattern?

Assert scan enable and shift the pattern into the chains, apply primary inputs, deassert scan enable and pulse the capture clock, then reassert scan enable and shift out the response while shifting in the next pattern.

VLS-279 · What is scan compression?

An on-chip decompressor feeds many short internal chains from a few scan inputs, and a compactor merges their outputs to a few scan outputs. This cuts test data volume and test time by large factors.

VLS-280 · What is the difference between launch-on-capture and launch-on-shift?

In launch-on-capture (broadside) the transition is launched by the first functional capture clock after shift. In launch-on-shift (skewed load) the last shift edge launches it, which needs an at-speed scan enable but usually gives higher coverage.

VLS-281 · What is fault collapsing?

Reducing the fault list by merging equivalent faults, those detected by the same tests (for example, stuck-at-0 on any input of an AND equals stuck-at-0 on its output). Dominance collapsing reduces it further.

VLS-282 · What are test points?

Extra control points (gates forcing a node to 0 or 1 in test mode) or observation points (flops capturing a node) inserted to improve the testability of hard-to-reach logic and raise coverage.

VLS-283 · What are common DFT design rules?

Flop clocks and asynchronous resets must be controllable from top-level pins in test mode. Avoid combinational loops, control or bypass internally generated clocks, keep tri-state buses from contention, and make latches transparent or scannable.

VLS-284 · Why is a lockup latch used in scan chains?

When a chain crosses from one clock domain to another with skew, the next flop could capture new data in the same shift cycle (hold violation). A lockup latch adds half a cycle of delay to keep the shift correct.

VLS-285 · What is IDDQ testing?

Measuring the quiescent supply current in a static state. Defects such as bridging shorts cause abnormally high current. It works less well at advanced nodes because normal leakage is high and variable.

VLS-286 · What is the March C− algorithm?

An MBIST algorithm: ⇕(w0); ⇑(r0,w1); ⇑(r1,w0); ⇓(r0,w1); ⇓(r1,w0); ⇕(r0). It needs 10N operations and detects stuck-at, transition, address-decoder and many coupling faults.

VLS-287 · How is scan chain length related to test time?

Each pattern needs about L shift cycles, where L is the longest chain, so balancing chains matters. Test cycles ≈ (patterns + 1) × L plus capture cycles. More chains reduce L but need more pins or compression.

VLS-288 · What are the JTAG TAP signals?

TCK (test clock), TMS (test mode select, which steps the 16-state TAP controller), TDI (test data in), TDO (test data out) and optional TRST (test reset).

FPGA, Analog/Mixed-Signal & Fabrication

VLS-289 · What are the main resources in a modern FPGA?

LUT-based logic blocks with flip-flops and carry chains, block RAM, DSP slices with multipliers and accumulators, clock management (PLLs/MMCMs) and global clock networks, programmable I/O and transceivers, and the programmable routing between them.

VLS-290 · How many configuration bits does a 6-input LUT need?

2⁶ = 64 bits, one for each input combination. It can implement any 6-input Boolean function, or in many architectures two smaller functions that share inputs.

VLS-291 · How does FPGA timing closure differ from ASIC timing closure?

In an FPGA cells are fixed, so routing delay often dominates. Closure relies on RTL pipelining, placement constraints and using dedicated resources (DSP, carry chains, BRAM registers) instead of sizing cells or building custom clock trees.

VLS-292 · What are SRAM, flash and antifuse FPGAs?

SRAM FPGAs are volatile and reprogrammable and need external configuration at power-up. Flash FPGAs are non-volatile and reprogrammable and come up instantly. Antifuse FPGAs are one-time programmable, non-volatile and radiation-tolerant.

VLS-293 · What is the LSB size of a 12-bit ADC with a 3.3 V reference?

LSB = Vref / 2ᴺ = 3.3 / 4096 ≈ 0.806 mV. The ideal quantization error is ±½ LSB, about ±0.4 mV.

VLS-294 · What is the ideal SNR of an N-bit ADC?

For a full-scale sine wave, SNR = 6.02·N + 1.76 dB. A 10-bit converter has about 62 dB. ENOB = (SINAD − 1.76) / 6.02 gives the effective number of bits from measurements.

VLS-295 · What are the blocks of a charge-pump PLL?

A phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator and a feedback divider. The output frequency is fout = N × fref.

VLS-296 · What is a current mirror?

A circuit that copies a reference current to other branches by sharing VGS between matched transistors. The output current is Iout = Iref × (W/L)out/(W/L)ref. Cascoding raises its output resistance.

VLS-297 · What are the main CMOS fabrication steps?

Wafer preparation, isolation (STI), well and channel implants, gate stack formation, source/drain implants and anneal, silicidation, contacts, then multiple metal layers with dielectric deposition, damascene copper and CMP. Each layer uses lithography and etch.

VLS-298 · What is the Poisson yield model?

Y = e^(−D·A), where D is defect density and A is die area. For D = 0.1 defects/cm² and A = 1 cm², Y = e^(−0.1) ≈ 90%.

VLS-299 · What is the difference between FEOL and BEOL?

Front end of line builds the transistors (isolation, wells, gates, source and drain). Back end of line builds the interconnect (contacts, vias, metal layers and dielectrics) above them.

VLS-300 · Why are differential circuits used in analog and high-speed design?

They reject common-mode noise and supply noise, double the signal swing, cancel even-order distortion, and in signalling reduce EMI. The cost is more devices and area.

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