Basic Electronics / VLSI interview questions

150 questions with answers (VLS-001 to VLS-150). Try each one aloud before reading the answer.

MOSFET Device Physics

VLS-001 · What is a MOSFET?

A metal-oxide-semiconductor field-effect transistor: a four-terminal device in which the gate voltage, acting through a thin insulator, creates or removes a conducting channel between source and drain. It is the basic switching element of CMOS chips.

VLS-002 · What are the four terminals of a MOSFET?

Gate, source, drain and body (bulk or substrate). The gate controls the channel, carriers flow from source to drain, and the body sets the substrate potential, which affects the threshold voltage.

VLS-003 · What is threshold voltage?

The gate-to-source voltage (Vt) at which a strong inversion layer forms under the gate and the transistor starts to conduct significantly. Typical values in modern nodes are roughly 0.2–0.5 V.

VLS-004 · What is the difference between enhancement-mode and depletion-mode MOSFETs?

An enhancement-mode device has no channel at VGS = 0 and needs gate voltage to turn on (normally off). A depletion-mode device has a built-in channel at VGS = 0 and needs reverse gate voltage to turn off (normally on). CMOS logic uses enhancement devices.

VLS-005 · What are the three regions of operation of a MOSFET?

Cut-off (VGS < Vt, almost no current), linear or triode (VGS > Vt and VDS < VGS − Vt, acts like a voltage-controlled resistor) and saturation (VDS ≥ VGS − Vt, current is roughly independent of VDS).

VLS-006 · What are the majority carriers in the channel of an NMOS and a PMOS?

An NMOS conducts through electrons in an inverted p-type body. A PMOS conducts through holes in an inverted n-type body (n-well). Electrons have higher mobility, so NMOS devices are stronger for the same size.

VLS-007 · What is the role of the gate oxide?

It insulates the gate from the channel so that almost no DC gate current flows, and it couples the gate field to the channel. Gate capacitance per unit area is Cox = εox/tox, so a thinner oxide gives more drive current.

VLS-008 · What is the body effect?

A rise in threshold voltage when the source-to-body voltage VSB increases. A reverse-biased body widens the depletion region, so more gate voltage is needed to invert the channel. It matters in stacked transistors whose sources are not at the rail.

VLS-009 · What is channel length modulation?

In saturation, increasing VDS moves the pinch-off point toward the source, shortening the effective channel and slightly increasing drain current. It is modelled as ID ∝ (1 + λ·VDS) and gives the transistor a finite output resistance.

VLS-010 · What is subthreshold conduction?

A small drain current that flows when VGS is below Vt, caused by carrier diffusion. It rises exponentially with VGS and is the main component of leakage in an "off" transistor.

VLS-011 · What is an inversion layer?

A thin layer under the gate oxide where the surface carrier type is flipped by the gate field, for example electrons in a p-type body. It forms the conducting channel between source and drain.

VLS-012 · What is a high-k metal gate (HKMG)?

A gate stack that replaces SiO₂ with a higher-permittivity dielectric (for example hafnium-based oxides) and polysilicon with a metal gate. High-k allows a physically thicker oxide with the same capacitance, cutting gate tunnelling leakage; the metal gate removes poly depletion.

VLS-013 · What is a FinFET?

A non-planar transistor whose channel is a thin vertical silicon fin with the gate wrapped around three sides. It is used in most leading-edge nodes from 22/16 nm onward.

CMOS Logic & Circuit Design

VLS-014 · What is CMOS, and why is it popular?

Complementary MOS uses an NMOS pull-down network and a PMOS pull-up network, so only one network conducts in steady state. This gives near-zero static power, full rail-to-rail swing, high noise margins and good scalability.

VLS-015 · How does a CMOS inverter work?

A PMOS connects the output to VDD and an NMOS connects it to ground, with both gates tied to the input. A low input turns on the PMOS (output high); a high input turns on the NMOS (output low).

VLS-016 · What is noise margin?

The amount of noise a logic level can tolerate without being misread. NMH = VOH − VIH and NML = VIL − VOL, where VIH and VIL are taken at the unity-gain points of the voltage transfer curve.

VLS-017 · What is the switching threshold (VM) of an inverter?

The input voltage at which Vout = Vin on the voltage transfer characteristic. It is set by the PMOS-to-NMOS strength ratio; equal strengths place VM near VDD/2.

VLS-018 · How is a 2-input CMOS NAND gate built?

Two NMOS transistors in series in the pull-down network and two PMOS transistors in parallel in the pull-up network. The output goes low only when both inputs are high.

VLS-019 · How is a 2-input CMOS NOR gate built?

Two NMOS transistors in parallel in the pull-down network and two PMOS transistors in series in the pull-up network. The output goes high only when both inputs are low.

VLS-020 · What are pull-up and pull-down networks?

The PMOS network that connects the output to VDD and the NMOS network that connects it to ground. In static CMOS they are logical duals: series in one corresponds to parallel in the other.

VLS-021 · What is a transmission gate?

An NMOS and a PMOS in parallel with complementary gate signals. Together they pass both strong 0 and strong 1, so it is used in multiplexers, latches and XOR gates.

VLS-022 · What is propagation delay?

The time from the 50% point of an input transition to the 50% point of the resulting output transition. Gate delay is often quoted as tp = (tpHL + tpLH)/2.

VLS-023 · What are rise time and fall time?

The time an output takes to go from 10% to 90% of its swing (rise) or from 90% to 10% (fall). Some libraries use 20%–80% thresholds instead. In timing tools this is called slew or transition.

VLS-024 · What is fan-out?

The number of gate inputs driven by one output. Higher fan-out means more load capacitance and therefore more delay.

VLS-025 · What are the components of power in a CMOS circuit?

Dynamic switching power from charging load capacitance, short-circuit power while both networks briefly conduct during a transition, and static leakage power (subthreshold, gate and junction leakage).

VLS-026 · What is a standard cell?

A pre-designed, pre-characterized logic gate or flip-flop with a fixed height and variable width, so cells can abut in rows. A library holds many functions and drive strengths, with timing, power and layout views.

Digital Design Fundamentals

VLS-027 · What is the difference between a latch and a flip-flop?

A latch is level-sensitive: it is transparent while its enable is active. A flip-flop is edge-triggered: it samples its input only at a clock edge.

VLS-028 · What is the difference between combinational and sequential logic?

Combinational logic outputs depend only on current inputs (gates, muxes, adders). Sequential logic outputs also depend on stored state (latches, flip-flops, FSMs) and usually need a clock.

VLS-029 · What is a multiplexer?

A circuit that selects one of 2ⁿ data inputs onto a single output using n select lines. A 2:1 mux implements Y = S'·A + S·B.

VLS-030 · What is the difference between a decoder and an encoder?

A decoder converts an n-bit code into one of 2ⁿ active outputs (for example 3-to-8). An encoder does the reverse, producing the binary code of the active input. A priority encoder handles several active inputs.

VLS-031 · What is Gray code?

A binary code in which successive values differ in exactly one bit, for example 00, 01, 11, 10. It is used in asynchronous FIFO pointers and rotary encoders to avoid multi-bit transition errors.

VLS-032 · What is the characteristic equation of a D flip-flop?

Q⁺ = D: on the active clock edge the output takes the value of D and holds it until the next edge.

VLS-033 · What is a JK flip-flop?

A flip-flop with characteristic Q⁺ = J·Q' + K'·Q. J = K = 1 toggles the output. A level-triggered JK suffers race-around; master-slave or edge-triggered designs fix this.

VLS-034 · What is the difference between synchronous and asynchronous (ripple) counters?

In a synchronous counter all flip-flops share one clock and change together. In a ripple counter each flip-flop is clocked by the previous stage's output, so delays accumulate and the outputs change at different times.

VLS-035 · What is a shift register?

A chain of flip-flops where each stage passes its value to the next on every clock. Variants are SISO, SIPO, PISO and PIPO; they are used for serial-parallel conversion, delays and scan chains.

VLS-036 · What is a universal gate?

A gate from which any Boolean function can be built. NAND and NOR are universal; for example, a NAND with tied inputs gives an inverter.

VLS-037 · What is a Karnaugh map?

A grid representation of a truth table in Gray-code order, so adjacent cells differ in one variable. Grouping adjacent 1s in powers of two gives a minimal sum-of-products expression.

VLS-038 · What is the difference between a half adder and a full adder?

A half adder adds two bits: S = A ⊕ B, C = A·B. A full adder also adds a carry-in: S = A ⊕ B ⊕ Cin, Cout = A·B + Cin·(A ⊕ B).

VLS-039 · What is two's complement representation?

A signed binary format in which a negative number is formed by inverting all bits and adding 1. An n-bit value covers −2ⁿ⁻¹ to 2ⁿ⁻¹ − 1, and addition and subtraction use the same hardware as unsigned arithmetic.

Verilog & SystemVerilog

VLS-040 · What is an HDL, and how do Verilog and VHDL differ?

A hardware description language describes concurrent hardware for simulation and synthesis. Verilog has C-like syntax and weak typing; VHDL has Ada-like syntax and strong typing. SystemVerilog extends Verilog with verification and design features.

VLS-041 · What is the difference between wire and reg in Verilog?

A wire is a net driven continuously by assign statements or module outputs. A reg is a variable assigned inside procedural blocks and holds its value between assignments. A reg does not necessarily become a flip-flop.

VLS-042 · What is a module in Verilog?

The basic building block of a design. It declares ports, internal signals and behaviour, and can instantiate other modules to build hierarchy.

VLS-043 · What is the difference between initial and always blocks?

An initial block runs once at time 0 and is mainly used in testbenches. An always block repeats forever, triggered by its event control, and models hardware.

VLS-044 · What are the four logic values in Verilog?

0 (logic low), 1 (logic high), x (unknown or conflicting) and z (high impedance, undriven).

VLS-045 · What is a sensitivity list?

The event list after @ that triggers an always block. always @(*) automatically includes all signals read in the block, which avoids incomplete lists in combinational logic.

VLS-046 · What is a continuous assignment?

An assign statement that drives a net and re-evaluates whenever any operand changes, modelling combinational logic, for example assign y = a & b;.

VLS-047 · What is the logic type in SystemVerilog?

A 4-state data type that can be assigned both procedurally and by continuous assignment (with a single driver). It replaces most uses of reg and wire.

VLS-048 · What are always_comb, always_ff and always_latch?

SystemVerilog procedural blocks that state design intent. Tools can warn if an always_comb infers a latch or an always_ff does not infer flops. always_comb also runs once at time 0 and has an implicit sensitivity list.

VLS-049 · What is a testbench?

Non-synthesizable code that instantiates the design under test (DUT), applies stimulus, and checks the outputs. It has no ports and usually generates clocks and resets.

VLS-050 · What is the difference between parameter and localparam?

Both are elaboration-time constants. A parameter can be overridden when the module is instantiated; a localparam cannot and is usually derived from parameters.

VLS-051 · What is a generate block?

A construct that creates repeated or conditional hardware at elaboration time using for or if with genvars and parameters, for example instantiating N copies of a cell.

VLS-052 · What is the difference between == and ===?

== is logical equality and returns x if either operand has x or z bits. === is case equality: it compares x and z literally and always returns 0 or 1. Only == is synthesizable.

RTL Design, FSMs & CDC

VLS-053 · What is RTL?

Register-transfer level: a description of a design as registers and the combinational logic that transforms data between them on each clock. It is the usual abstraction for synthesizable Verilog and VHDL.

VLS-054 · What is a finite state machine?

A sequential circuit with a finite set of states, a state register, next-state logic and output logic. It moves between states based on inputs at each clock edge.

VLS-055 · What is the difference between Moore and Mealy machines?

In a Moore machine outputs depend only on the current state. In a Mealy machine outputs depend on the state and current inputs, so it reacts one cycle earlier and often needs fewer states, but its outputs can glitch.

VLS-056 · What are the common FSM state encodings?

Binary (log₂N flops), one-hot (N flops, one bit set), and Gray (adjacent states differ by one bit). One-hot gives simple, fast next-state logic and suits FPGAs; binary uses fewer flops.

VLS-057 · What is a clock domain crossing (CDC)?

A signal path that goes from logic clocked by one clock to logic clocked by another clock with an unrelated or asynchronous phase. Such paths need synchronizers because normal timing checks do not apply.

VLS-058 · What is the difference between synchronous and asynchronous reset?

A synchronous reset is sampled only on the clock edge and acts like data. An asynchronous reset forces the flop immediately, regardless of the clock. Asynchronous reset works without a clock but its release must be synchronized.

VLS-059 · What is a FIFO?

A first-in-first-out buffer with write and read pointers and full and empty flags. It decouples producers and consumers working at different rates or in different clock domains.

VLS-060 · What is pipelining?

Splitting a long combinational path into stages separated by registers. It raises clock frequency and throughput at the cost of latency, area and extra registers.

VLS-061 · What causes an unintended latch in RTL?

A combinational always block in which some output is not assigned on every path, for example an if without else or a case without a default. The tool must hold the old value, which needs a latch.

VLS-062 · What is a valid/ready handshake?

A flow-control protocol where the sender asserts valid when data is available and the receiver asserts ready when it can accept. A transfer happens on a clock edge when both are high.

VLS-063 · What is a reset synchronizer?

A two-flop circuit that lets reset assert asynchronously but releases it synchronously to the destination clock. This avoids recovery and removal violations when reset deasserts.

VLS-064 · What is the difference between a datapath and a control path?

The datapath holds and processes data (registers, ALUs, muxes, memories). The control path, often an FSM, generates the select, enable and load signals that steer the datapath.

VLS-065 · What is an arbiter?

A circuit that grants access to a shared resource to one of several requesters. Common schemes are fixed priority and round-robin.

Functional Verification (UVM, Assertions, Coverage)

VLS-066 · What is functional verification?

Checking that the RTL behaves as the specification says before tape-out, using simulation, formal methods, emulation and prototyping. It typically takes more effort than design itself.

VLS-067 · What is the difference between simulation and formal verification?

Simulation applies chosen input vectors and checks results, so it only covers what it exercises. Formal verification uses mathematical analysis to prove or disprove properties for all legal inputs, within the bounds of the analysis.

VLS-068 · What is UVM?

The Universal Verification Methodology: a standardized SystemVerilog class library (IEEE 1800.2) for building reusable, layered, constrained-random testbenches with components such as agents, sequences and scoreboards.

VLS-069 · What does a UVM agent contain?

A sequencer that supplies transactions, a driver that converts them to pin activity on the DUT interface, and a monitor that samples the interface and broadcasts observed transactions. A passive agent contains only the monitor.

VLS-070 · What is a scoreboard?

A testbench component that compares the DUT's actual outputs with expected outputs, usually from a reference model, and reports mismatches.

VLS-071 · What is the difference between code coverage and functional coverage?

Code coverage is measured automatically from the RTL (line, branch, toggle, condition, FSM). Functional coverage is user-defined with covergroups and measures whether specified features and scenarios were exercised.

VLS-072 · What is a SystemVerilog assertion (SVA)?

A statement of expected behaviour that is checked during simulation or formally. Immediate assertions check at one point in procedural code; concurrent assertions check temporal properties over clock cycles.

VLS-073 · What is constrained-random verification?

Generating random stimulus that obeys legal constraints, so many scenarios, including unexpected ones, are hit automatically. Coverage measures progress and checkers detect bugs.

VLS-074 · What are covergroups and coverpoints?

A covergroup is a SystemVerilog construct that samples variables at defined events. Each coverpoint tracks the values of one expression in bins; crosses track combinations of coverpoints.

VLS-075 · What is a transaction in UVM?

A class object, usually extended from uvm_sequence_item, that represents one abstract operation such as a bus write with address and data. Sequences create transactions and drivers convert them to signals.

VLS-076 · What is a verification plan?

A document that lists the features to verify, how each will be checked (test, assertion, formal), and the coverage goals that define completion. It is derived from the specification.

VLS-077 · What is a regression?

Running a large suite of tests, often with many random seeds, after every change to confirm that new code has not broken existing behaviour.

VLS-078 · What is a reference model?

A high-level, independently written model of expected DUT behaviour, often in SystemVerilog, C or C++. The scoreboard compares its outputs with the DUT's.

Static Timing Analysis

VLS-079 · What is static timing analysis (STA)?

A method that checks every timing path in a design against setup, hold and other constraints without applying input vectors. It is exhaustive and fast compared with timing simulation, but it does not check function.

VLS-080 · What are the four basic types of timing path?

Input port to register, register to register, register to output port, and input port to output port (pure combinational). Each path runs from a startpoint to an endpoint.

VLS-081 · What is slack?

The margin by which a path meets its requirement. Setup slack = required time − arrival time; hold slack = arrival time − required time. Positive slack meets timing; negative slack is a violation.

VLS-082 · What are the startpoint and endpoint of a timing path?

A startpoint is a clock pin of a sequential element or an input port where data is launched. An endpoint is a data input of a sequential element or an output port where data is captured.

VLS-083 · What is clock latency?

The delay from the clock source to a flop's clock pin. Source latency runs from the clock origin to the clock definition point; network latency runs from the definition point through the clock tree to the sink.

VLS-084 · What is clock jitter?

The deviation of a clock edge from its ideal position, varying from cycle to cycle. In STA it is included in clock uncertainty and reduces the time available for data.

VLS-085 · What is a false path?

A path that exists structurally but can never be sensitized functionally, or whose timing does not matter, for example between asynchronous clocks or static configuration registers. It is excluded with set_false_path.

VLS-086 · What is a multicycle path?

A path whose data is intentionally allowed more than one clock cycle to propagate, because the capture register is enabled only every N cycles. It is constrained with set_multicycle_path.

VLS-087 · What is a critical path?

The path with the worst (most negative or smallest) setup slack. It limits the maximum operating frequency of the design.

VLS-088 · What are PVT corners?

Combinations of process (slow, typical, fast devices), supply voltage and temperature at which timing is analysed. Setup is usually checked at slow corners and hold at fast corners.

VLS-089 · What is SDC?

Synopsys Design Constraints: a Tcl-based format that specifies clocks, input and output delays, exceptions, loads and design rules for synthesis and STA tools.

VLS-090 · What is a Liberty (.lib) file?

A text library file that describes each standard cell's pins, function, timing arcs, setup and hold constraints, power and capacitance, usually as tables indexed by input slew and output load at one PVT corner.

Logic Synthesis

VLS-091 · What is logic synthesis?

The automatic translation of RTL into an optimized gate-level netlist of standard cells from a target library, meeting timing, area and power constraints.

VLS-092 · What is a netlist?

A description of a circuit as instances of gates or cells and the nets that interconnect their pins. Synthesis produces a gate-level netlist, usually in Verilog.

VLS-093 · What are the inputs to synthesis?

RTL source files, technology libraries (.lib or .db), design constraints (SDC), and optionally power intent (UPF), DFT setup and physical information such as floorplan data.

VLS-094 · What is technology mapping?

The synthesis step that implements the optimized generic logic using actual cells from the target library, choosing functions and drive strengths that meet constraints.

VLS-095 · What is elaboration in synthesis?

Building the design hierarchy from parsed RTL: resolving parameters, unrolling generate blocks, and inferring generic registers, operators and logic before optimization.

VLS-096 · What does QoR mean in synthesis?

Quality of results: the metrics used to judge a netlist, mainly worst and total negative slack, area, cell count, leakage and dynamic power, and design-rule violations.

VLS-097 · What is a wire load model?

A statistical table estimating net capacitance and resistance from fan-out and block size, used by synthesis when no placement data exists. It is inaccurate at deep sub-micron nodes, so physical-aware synthesis is often used instead.

VLS-098 · What is logic equivalence checking (LEC)?

A formal check that two representations of a design, such as RTL and netlist or pre- and post-ECO netlists, are functionally identical. It matches registers and compares the logic cones between them.

VLS-099 · Which Verilog constructs are not synthesizable?

Delays (#10), initial blocks in most ASIC flows, $display and other system tasks, fork-join, force/release, file I/O and most testbench-only SystemVerilog classes. Unbounded loops are also not synthesizable.

VLS-100 · What is a dont_touch attribute?

A constraint that tells synthesis or place-and-route not to optimize, resize or remove a particular cell, net or module, for example hand-instantiated synchronizers or clock cells.

VLS-101 · What is the difference between flat and hierarchical synthesis?

Flat synthesis removes module boundaries so logic can be optimized across them, which often gives better QoR. Hierarchical synthesis keeps boundaries, which eases debug, ECOs, reuse and runtime on large designs.

VLS-102 · What is the difference between a generic and a mapped netlist?

A generic netlist uses technology-independent primitives such as GTECH gates and operators after elaboration. A mapped netlist uses real library cells after technology mapping.

Physical Design (Floorplan, Placement, CTS, Routing, Signoff)

VLS-103 · What is physical design?

The steps that turn a gate-level netlist into a manufacturable layout: floorplanning, power planning, placement, clock tree synthesis, routing, and physical and timing signoff.

VLS-104 · What is floorplanning?

Deciding the die and core size, I/O pin positions, macro placement, power-domain regions and blockages. A good floorplan sets up routability and timing for the rest of the flow.

VLS-105 · What is a hard macro?

A pre-built block with fixed layout, such as an SRAM, PLL or analog IP, delivered with abstract (LEF) and timing (.lib) views. The tool places it but cannot change its contents.

VLS-106 · What is placement?

Assigning legal locations in the standard-cell rows to every cell in the netlist so that wirelength, timing and congestion are optimized.

VLS-107 · What is clock tree synthesis (CTS)?

Building a buffered clock distribution network from the clock source to all sinks so that skew, insertion delay and transition stay within targets.

VLS-108 · What is the difference between global and detailed routing?

Global routing assigns nets to coarse routing regions (g-cells) and layers to plan resources and estimate congestion. Detailed routing creates exact wire and via geometry that obeys design rules.

VLS-109 · What is a power delivery network (PDN)?

The grid of power and ground rings, straps and rails, plus vias, that carries supply current from bumps or pads to every cell with acceptable IR drop and electromigration limits.

VLS-110 · What is GDSII?

A binary stream format for layout geometry organized by layers and cells. It is the traditional final database sent to the foundry for mask making. OASIS is a newer, more compact alternative.

VLS-111 · What is DRC?

Design rule checking: verifying that layout geometry obeys foundry rules such as minimum width, spacing, enclosure and density, so that the design can be manufactured reliably.

VLS-112 · What is LVS?

Layout versus schematic: extracting devices and connectivity from the layout and comparing them with the netlist to confirm that the layout implements the intended circuit.

VLS-113 · What is a LEF file?

Library Exchange Format: an abstract physical description giving each cell's or macro's size, pin locations and blockages, plus technology data such as layers, vias and routing rules.

VLS-114 · What is core utilization?

The fraction of core area occupied by standard cells and macros: utilization = cell area / core area. Typical starting values are around 60–80%, leaving space for buffering and routing.

Low-Power Design

VLS-115 · Why is low-power design important?

Power limits battery life, heat, packaging cost and reliability. At advanced nodes, power density, not transistor count, often limits performance.

VLS-116 · What is clock gating?

Disabling the clock to a group of registers when they do not need to update, removing switching power in the clock tree and the gated logic. It is usually done with an integrated clock-gating (ICG) cell.

VLS-117 · What is power gating?

Cutting the supply to an idle block with header or footer switch transistors so that its leakage nearly disappears. It needs isolation, often retention, and controlled power-up sequencing.

VLS-118 · What are multi-Vt cells?

Library variants of the same cell built with different threshold voltages (for example high, standard and low Vt). Low-Vt cells are fast but leaky; high-Vt cells are slow with low leakage.

VLS-119 · What is DVFS?

Dynamic voltage and frequency scaling: lowering voltage and frequency together when performance demand is low. Because dynamic power scales with V²·f, it saves power strongly.

VLS-120 · What is a voltage island?

A region of the chip that runs from its own supply voltage, different from other regions. Multi-voltage design runs each block at the lowest voltage that meets its performance needs.

VLS-121 · What is a level shifter?

A cell that converts a signal from one voltage domain's swing to another's, especially low-to-high, so the receiving gate switches fully and does not leak or fail.

VLS-122 · What is an isolation cell?

A cell that clamps the outputs of a powered-down domain to a known value (0, 1 or latched) so that floating signals do not cause crowbar current or wrong logic in powered-on domains.

VLS-123 · What is a retention flip-flop?

A flop with an extra always-on storage element that saves its state before power gating and restores it on power-up, so the block need not reinitialize.

VLS-124 · What is UPF?

The Unified Power Format (IEEE 1801): a Tcl-based way to describe power intent, including power domains, supplies, switches, isolation, level shifting and retention, separately from the RTL.

VLS-125 · What is leakage power?

Power drawn when a circuit is not switching, caused by subthreshold, gate-oxide tunnelling and junction leakage currents. It rises with temperature and with lower threshold voltage.

VLS-126 · What is the difference between header and footer power switches?

A header is a PMOS switch between VDD and the block's virtual VDD. A footer is an NMOS switch between the virtual ground and VSS. Footers are smaller for the same on-resistance; headers are more common in practice.

Design for Testability

VLS-127 · What is the difference between testing and verification?

Verification checks that the design is correct before fabrication. Manufacturing test checks that each fabricated chip is free of physical defects, using patterns applied on automatic test equipment (ATE).

VLS-128 · What is a stuck-at fault?

A fault model in which a net is assumed to be permanently fixed at logic 0 (stuck-at-0) or logic 1 (stuck-at-1). It is the basic model for ATPG and fault coverage.

VLS-129 · What are controllability and observability?

Controllability is how easily a node can be set to 0 or 1 from inputs. Observability is how easily its value can be seen at outputs. DFT improves both.

VLS-130 · What is a scan flip-flop?

A flip-flop with a multiplexer at its D input selecting between functional data and a scan input (SI), controlled by scan enable (SE). In scan mode the flops form a shift register.

VLS-131 · What is ATPG?

Automatic test pattern generation: software that creates input patterns and expected outputs that detect modelled faults, for example stuck-at and transition faults, through scan chains.

VLS-132 · What is fault coverage?

The percentage of modelled faults detected by the test patterns: detected faults / total faults × 100. Test coverage excludes faults proven untestable from the denominator.

VLS-133 · What is BIST?

Built-in self-test: on-chip logic that generates test patterns (often with an LFSR) and compresses responses (with a MISR), so the chip can test itself with little ATE support.

VLS-134 · What is MBIST?

Memory built-in self-test: an on-chip controller that runs march algorithms on embedded memories to detect cell, address-decoder and coupling faults, often with repair support.

VLS-135 · What is JTAG boundary scan?

The IEEE 1149.1 standard: a test access port (TAP) and a chain of boundary-scan cells at the I/O pins, used to test board interconnect and access on-chip test and debug logic.

VLS-136 · What are shift and capture modes in scan test?

In shift mode (SE = 1) patterns are serially loaded into and unloaded from scan chains. In capture mode (SE = 0) one or more functional clocks capture the combinational logic response into the flops.

VLS-137 · What is a transition fault?

A delay fault model in which a node is slow to rise or slow to fall, so the transition does not reach the capture flop within one at-speed cycle. It is tested with launch and capture pulses.

VLS-138 · What is yield?

The fraction of manufactured dies that work to specification. It is set by defect density, die area, process variation and design margins.

FPGA, Analog/Mixed-Signal & Fabrication

VLS-139 · What is the difference between an ASIC and an FPGA?

An ASIC is custom-fabricated for one application: high performance, low power and low unit cost, but high NRE and no changes after tape-out. An FPGA is reconfigurable with fast time-to-market and low NRE, but it is slower, more power-hungry and costlier per unit.

VLS-140 · What is Moore's law?

Gordon Moore's observation that the number of transistors on a chip doubles roughly every two years. It is an economic and technology trend, not a physical law.

VLS-141 · What is a LUT in an FPGA?

A look-up table: a small memory with k address inputs storing 2ᵏ configuration bits. It can implement any Boolean function of k inputs; modern FPGAs commonly use 6-input LUTs.

VLS-142 · What is a configurable logic block (CLB)?

The basic FPGA logic tile, made of LUTs, flip-flops, carry chains and local multiplexers, connected to other blocks through programmable routing.

VLS-143 · What is an FPGA bitstream?

The configuration file that sets every LUT, flip-flop mode, routing switch and I/O setting in an FPGA. It is loaded at power-up into configuration memory.

VLS-144 · What are an ADC and a DAC?

An analog-to-digital converter samples and quantizes an analog signal into digital codes. A digital-to-analog converter turns digital codes into an analog voltage or current.

VLS-145 · What is a PLL?

A phase-locked loop: a feedback system that locks an oscillator's phase to a reference clock. It is used to multiply clock frequency, generate clocks and reduce skew.

VLS-146 · What is the difference between a wafer and a die?

A wafer is a thin slice of single-crystal silicon (commonly 300 mm diameter) on which many chips are fabricated. A die is one chip cut from the wafer.

VLS-147 · What is photolithography?

The process of transferring circuit patterns from a mask onto a wafer by exposing a light-sensitive photoresist, developing it, and then etching or implanting through the patterned resist.

VLS-148 · What is a technology node?

A label for a process generation, such as 28 nm, 7 nm or 3 nm. At modern nodes it is a marketing name for density and performance, not a physical gate length.

VLS-149 · What is a bandgap reference?

A circuit that produces a stable voltage, about 1.2 V for silicon, that is nearly independent of temperature and supply. It adds a PTAT voltage to a CTAT base-emitter voltage.

VLS-150 · What is ion implantation?

A doping process in which ionized dopant atoms such as boron, phosphorus or arsenic are accelerated into the wafer. Dose and energy control concentration and depth; annealing repairs damage and activates dopants.

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