Advanced Electronics / VLSI interview questions

125 questions with answers (VLS-301 to VLS-425). Try each one aloud before reading the answer.

MOSFET Device Physics

VLS-301 · Your design's leakage is three times the estimate at the hot corner. How would you investigate and reduce it?

Break leakage down by cell type and Vt flavour using power analysis at the right corner (fast-fast, 125 °C), check for low-Vt over-use and unexpected always-on blocks, and look for GIDL or gate leakage hotspots. Swap non-critical cells to high-Vt, add power gating or body biasing for idle blocks, and re-verify timing.

VLS-302 · How does mobility degradation at high gate fields affect drive current, and how is it modelled?

Strong vertical fields push carriers against the oxide interface, increasing surface scattering and lowering effective mobility, so current grows more slowly than the square law predicts. Compact models (BSIM) use mobility reduction parameters as functions of effective field; strain engineering offsets it.

VLS-303 · How would you choose between bulk planar, FD-SOI and FinFET for a low-power IoT chip?

FD-SOI offers low leakage, good analog/RF and strong back-biasing for adaptive power at lower cost, ideal for IoT. FinFET gives the best density and performance but costs more; bulk planar at mature nodes is cheapest but leakier. Compare cost, power, analog needs and IP availability.

VLS-304 · How do you account for device ageing (NBTI, HCI) in timing signoff?

Use ageing-aware libraries or derates that shift threshold voltage and drive current over the target lifetime and mission profile (voltage, temperature, activity), and close timing with that margin. Critical paths with high stress may need extra slack or adaptive voltage.

VLS-305 · How does strain engineering improve transistor performance?

Tensile strain in the NMOS channel increases electron mobility and compressive strain in PMOS (e.g. SiGe source/drain) increases hole mobility, raising drive current without shrinking dimensions. Stress liners and embedded SiGe are common techniques.

VLS-306 · How do you calculate the threshold voltage shift due to a body bias of 0.5 V?

ΔVt = γ(√(2φF + VSB) − √(2φF)). With γ = 0.4 V½ and 2φF = 0.7 V: √1.2 − √0.7 = 1.095 − 0.837 = 0.258, so ΔVt ≈ 0.4 × 0.258 ≈ 0.10 V.

VLS-307 · Why does a FinFET's drive current scale in discrete steps, and how does it affect design?

Width is quantised by the number of fins (effective width ≈ fins × (2·fin height + fin thickness)), so device sizes come in discrete steps. Designers size gates by fin count, and analog matching uses fin-count ratios rather than arbitrary widths.

VLS-308 · How do you reduce random dopant fluctuation effects in small transistors?

Use undoped or lightly doped channels with threshold voltage set by gate work function (as in FinFET and FD-SOI), larger device areas for matching-critical analog circuits, and statistical design margins.

VLS-309 · How does self-heating affect FinFET reliability and timing?

Fins are thermally isolated, so current raises local temperature, reducing mobility and accelerating ageing and electromigration. Models include self-heating, and designers limit current density on high-activity nets.

VLS-310 · How would you characterise a new transistor for a compact model?

Measure I-V and C-V across geometries, temperatures and biases, extract BSIM parameters by fitting, validate against ring oscillator and circuit measurements, and add statistical variation models.

VLS-311 · How does gate-all-around improve on FinFET electrostatics?

The gate surrounds the channel on all sides, improving control of the channel potential, reducing short-channel effects and DIBL, and allowing continuous width tuning via nanosheet width.

CMOS Logic & Circuit Design

VLS-312 · How would you size a chain of inverters to drive a 2 pF load from a gate with 5 fF input capacitance?

Total effort F = Cload/Cin = 400. Optimum stage effort is about 4, so N ≈ log₄(400) ≈ 4.3, giving 4 stages with each stage about 400^(1/4) ≈ 4.5 times larger than the previous one.

VLS-313 · How do you choose between static CMOS and dynamic logic for a high-speed block?

Dynamic logic is faster and smaller for wide OR/NOR functions but has charge sharing, leakage, noise sensitivity and higher clock power. Static CMOS is robust and easier to verify; dynamic logic is used only where speed justifies the design effort.

VLS-314 · How do you design a low-skew clock buffer for high fan-out?

Use balanced H-tree or mesh distribution, size buffers for equal rise and fall delays, match wire lengths and loads, and use shielding to reduce crosstalk and jitter.

VLS-315 · How do you improve the read stability of a 6T SRAM cell?

Increase the cell ratio (pull-down to access transistor strength), use read-assist techniques (wordline underdrive), or switch to an 8T cell with a separate read port that isolates the storage node.

VLS-316 · A 6T SRAM fails to write at low voltage. What assist techniques would you use?

Writability depends on the access transistor overpowering the pull-up. Use negative bitline write assist, lowered cell supply (VDD collapse) during write, wordline overdrive, or weaker pull-up PMOS sizing. Verify read stability isn't degraded by the change.

VLS-317 · How would you design a level-restoring circuit after an NMOS pass-transistor network?

Since NMOS passes a degraded high (VDD − Vt), follow it with an inverter plus a weak PMOS keeper fed back from the inverter output to pull the node fully to VDD. Size the keeper weak enough that the pass network can still pull the node low.

VLS-318 · How do you reduce power in a high-fanout bus driving long wires?

Lower swing (low-swing signalling), bus encoding to reduce transitions (bus-invert, Gray code), repeaters sized for energy rather than minimum delay, and clock gating on unused cycles.

VLS-319 · How would you implement a fast 64-bit adder?

Use a parallel-prefix structure (Kogge-Stone for speed, Brent-Kung or Han-Carlson for area and wiring trade-offs), with carry-select or sparse tree variants. Logarithmic depth gives much lower delay than ripple-carry.

VLS-320 · How do you minimise crosstalk-induced delay on a critical wire?

Increase spacing, add shielding with ground wires, route on less congested layers, reduce coupling length with neighbours switching in opposite directions, upsize drivers, and use timing windows to avoid simultaneous switching.

VLS-321 · How would you design a domino logic gate to avoid charge sharing?

Use a keeper on the dynamic node, precharge internal nodes, reorder transistors so the input that switches last is closest to the output, and size the evaluation network carefully.

VLS-322 · How do you size a repeater chain for a long interconnect?

Optimal repeater spacing and size balance wire RC delay with gate delay; delay grows linearly with wire length when repeaters are optimally inserted, rather than quadratically for an unbuffered wire.

Digital Design Fundamentals

VLS-323 · How would you design a 32-bit multiplier for a high clock frequency?

Generate partial products with Booth radix-4 encoding to halve their number, reduce them with a Wallace or Dadda tree of compressors, and finish with a fast prefix adder. Pipeline the tree to meet the clock period, trading latency for throughput.

VLS-324 · How do you design a circuit to detect the leading one in a 32-bit word?

Use a hierarchical priority encoder: split the word into groups, find the leading one within each group and the leading non-zero group in parallel, then combine. This gives logarithmic delay instead of a long priority chain.

VLS-325 · How would you implement division in hardware?

Options include restoring/non-restoring iterative division (one bit per cycle), SRT radix-4 division with redundant quotient digits for speed, or Newton-Raphson reciprocal approximation using the multiplier. The choice trades area, latency and throughput.

VLS-326 · How do you design a counter that counts in Gray code?

Maintain a binary counter internally and convert to Gray (g = b ^ (b >> 1)), or design a direct Gray-code sequence with logic that toggles only one bit per step. Gray counters are used for asynchronous FIFO pointers.

VLS-327 · How would you build a barrel shifter for 32-bit data?

Use log₂(32) = 5 stages of multiplexers, each shifting by a power of two (1, 2, 4, 8, 16) controlled by one shift-amount bit. Rotates and arithmetic shifts are added with extra mux inputs.

VLS-328 · How do you implement a CRC generator in hardware?

Use a linear feedback shift register based on the generator polynomial; for parallel data, derive XOR equations to process multiple bits per clock cycle.

VLS-329 · How do you design a fixed-point datapath to avoid overflow?

Analyse signal ranges, choose word lengths and guard bits, use saturation arithmetic where needed, and simulate with worst-case inputs.

VLS-330 · How would you build a clock divider by 3 with a 50% duty cycle?

Use a mod-3 counter on the rising edge and another sampled on the falling edge, then OR (or combine) the outputs so the divided clock is high for 1.5 input cycles.

VLS-331 · How would you design a round-robin arbiter for 8 requesters?

Keep a pointer to the last granted requester, mask requests at or below it, and use a priority encoder on the masked vector; if no masked request exists, fall back to the unmasked vector. Update the pointer after each grant so every requester is served fairly within 8 cycles.

VLS-332 · How do you implement an LFSR-based pseudo-random generator with maximal length?

Use a shift register whose feedback taps follow a primitive polynomial (for example x¹⁶ + x¹⁴ + x¹³ + x¹¹ + 1 for 16 bits), giving a sequence of 2ⁿ − 1 states. Avoid the all-zero lock-up state by seeding with a non-zero value.

VLS-333 · How would you compute a population count (number of ones) in a 64-bit word quickly?

Use a tree of adders: first count pairs of bits, then add the 2-bit counts, then 4-bit counts and so on (a carry-save adder tree), giving logarithmic delay. Compressor trees reduce delay further.

Verilog & SystemVerilog

VLS-334 · A simulation passes but the synthesised netlist fails. What RTL issues would you look for?

Incomplete sensitivity lists, blocking assignments in sequential logic, initial blocks or delays relied on for behaviour, X-propagation masked in simulation (X-optimism), full_case/parallel_case pragmas, and uninitialised registers. Run gate-level simulation and LEC to locate mismatches.

VLS-335 · How do you write parameterised, reusable RTL for a FIFO?

Use parameters for width and depth, $clog2 for pointer sizes, generate blocks for optional features, and interfaces for clean port bundles. Avoid hard-coded constants and document assumptions with assertions.

VLS-336 · How do you avoid X-propagation issues in RTL simulation?

Reset all control registers, avoid relying on X-optimistic constructs (if/case on X evaluating to the else branch), use X-pessimism checks or tools that model X more accurately, and add assertions that key signals are never X after reset.

VLS-337 · How would you model a dual-port RAM in synthesisable SystemVerilog?

Declare a memory array with always_ff blocks for each port's write and registered read, with parameters for width and depth. Match the coding template recommended by the vendor so synthesis infers block RAM instead of flip-flops.

VLS-338 · How do you use SystemVerilog classes in a testbench?

Classes model transactions, generators, drivers and scoreboards with inheritance and polymorphism, use randomisation with constraints, and enable reusable, layered testbench architectures like UVM.

VLS-339 · How would you write a self-checking testbench for an ALU?

Generate random and directed operands and opcodes, compute expected results with a reference model in the testbench, compare each output, report mismatches with details, and collect functional coverage of opcodes and corner cases.

VLS-340 · How do you prevent race conditions between testbench and DUT?

Use non-blocking assignments for sequential logic, clocking blocks to sample and drive signals at defined points, program blocks or reactive regions for testbench code, and avoid driving signals at the same time step as the DUT samples them.

VLS-341 · How do you write RTL that infers clock gating cleanly?

Use enable conditions in sequential blocks (if (en) q <= d;), let synthesis insert integrated clock gating cells, and avoid manually gating clocks with combinational logic that can glitch.

VLS-342 · How do you code a parameterised mux with N inputs?

Use an array of inputs and index with the select signal (assign y = in[sel];), which synthesises to a multiplexer tree; add assertions for out-of-range selects when N isn't a power of two.

VLS-343 · How would you debug a simulation that hangs?

Check for zero-delay loops (combinational feedback), missing clock generation, infinite loops in testbench code, and objections not being dropped in UVM; use simulator debug tools to find the active processes.

VLS-344 · How do you use SystemVerilog assertions to verify a FIFO?

Write assertions that writes never occur when full, reads never occur when empty, count never exceeds depth, and data read matches data written in order (with a model).

RTL Design, FSMs & CDC

VLS-345 · How would you design an asynchronous FIFO between a 200 MHz and a 50 MHz domain?

Use a dual-port RAM with write and read pointers in their own domains, convert pointers to Gray code, synchronise each into the other domain with two-flop synchronisers, and compute full and empty flags from the synchronised pointers. Size depth for the worst-case burst and rate mismatch.

VLS-346 · How do you calculate the minimum depth of an async FIFO for a burst?

Depth ≥ burst length × (1 − read rate/write rate), plus margin for synchroniser latency. For example, a burst of 120 words written at 100 MHz and read at 80 MHz (one word per cycle each): 120 × (1 − 80/100) = 24 words, plus a few entries for pointer synchronisation, so 32 is a safe choice.

VLS-347 · How would you transfer a multi-bit configuration value safely across clock domains?

Hold the data stable, then send a single-bit request synchronised to the destination (handshake or toggle), and sample the data once the request is seen; acknowledge back. Alternatively use an async FIFO or Gray-coded values if they only change by one step.

VLS-348 · How do you choose MTBF for a synchroniser and decide if two flops are enough?

MTBF = e^(tr/τ)/(T0·fclk·fdata), where tr is the resolution time available. At high frequencies or for critical systems with long lifetimes, calculate MTBF with library τ and T0; if it is too low, add a third flop or reduce frequency.

VLS-349 · How do you design an FSM to be robust against illegal states?

Define a default branch that returns illegal states to a safe state, use safe FSM encoding options in synthesis, add parity or one-hot checks for safety-critical designs, and include assertions to detect illegal states in simulation.

VLS-350 · How would you design a reset scheme for a multi-clock SoC?

Use asynchronous assertion and synchronous de-assertion per clock domain with reset synchronisers, define reset sequencing between domains, avoid reset-domain-crossing issues, and verify with RDC tools.

VLS-351 · How do you pipeline a design that fails timing by 30%?

Identify long combinational paths, insert pipeline registers at balanced points, retime logic, and handle the added latency in control logic and interfaces with valid signals. Re-verify functionality and throughput.

VLS-352 · How do you design a credit-based flow control interface?

The receiver advertises buffer credits; the sender decrements credits when sending and stops at zero, and the receiver returns credits as buffers free up. This avoids overflow with long round-trip latencies.

VLS-353 · How do you handle back-pressure in a valid/ready pipeline?

Use skid buffers so that when ready deasserts, data in flight is captured without loss, and avoid combinational paths from ready through multiple stages that limit timing.

VLS-354 · How do you design glitch-free clock switching between two asynchronous clocks?

Use a synchronised enable for each clock with cross-coupled feedback so one clock is disabled before the other is enabled, and gate clocks with integrated clock gating cells.

VLS-355 · How would you verify CDC correctness in a design?

Run structural CDC tools to find unsynchronised crossings, reconvergence and multi-bit issues, add protocol assertions, and use CDC-aware simulation with metastability injection.

Functional Verification (UVM, Assertions, Coverage)

VLS-356 · How would you build a UVM environment for an AXI-based IP?

Create AXI master and slave agents (sequencer, driver, monitor) with a configurable interface, a reference model and scoreboard that compares transactions, a coverage collector for burst types, sizes, IDs and responses, and virtual sequences coordinating multiple agents. Reuse VIP where available.

VLS-357 · Coverage stalls at 85% after weeks of random tests. What would you do?

Analyse coverage holes to see if they are unreachable (exclude with justification) or need directed constraints, adjust constraint distributions, write targeted sequences, and consider formal tools to reach or prove unreachability of remaining bins.

VLS-358 · How do you decide between simulation and formal verification for a block?

Formal is best for control-heavy blocks with deep corner cases (arbiters, FIFOs, protocol checkers) where exhaustive proof is feasible; simulation suits datapath-heavy and large system-level verification. Many teams use both.

VLS-359 · How do you write a scoreboard that handles out-of-order transactions?

Store expected transactions in associative arrays keyed by ID, match actual responses by ID rather than order, and check for missing or extra transactions at end of test.

VLS-360 · How do you debug a failing regression test efficiently?

Reproduce with the same seed, find the first point of divergence with logs and waveforms, use assertions to localise the issue, and determine whether the bug is in the DUT, testbench or reference model.

VLS-361 · How would you verify a cache controller?

Build a reference memory model and scoreboard, generate random and directed access patterns (hits, misses, evictions, write-backs, same-set conflicts), check coherency and ordering with assertions, and collect coverage on states, transitions and corner cases such as simultaneous eviction and fill.

VLS-362 · How do you measure verification completeness before tapeout?

Combine signed-off code coverage (line, branch, toggle, FSM), functional coverage closure against the verification plan, assertion coverage, passing regressions with many seeds, bug-rate trend flattening, and formal proofs on critical blocks. Waive uncovered items with documented reasons.

VLS-363 · How would you use emulation or FPGA prototyping in verification?

Map the design to an emulator or FPGA to run billions of cycles for software bring-up, OS boot and long scenarios that simulation can't reach, while keeping simulation for detailed debug. Transactors connect the prototype to software models or real interfaces.

VLS-364 · How do you verify low-power behaviour (power-aware simulation)?

Simulate with the UPF so power-down domains corrupt outputs, check isolation and retention behaviour on power-up and power-down sequences, and use assertions on power state transitions.

VLS-365 · How do you write an SVA property to check a request is eventually granted?

Use property p; @(posedge clk) disable iff (!rst_n) req |-> s_eventually gnt; endproperty, or bound the latency with req |-> ##[1:16] gnt for a practical simulation check. Unbounded liveness is best proven formally.

Static Timing Analysis

VLS-366 · A design fails hold timing on many paths after CTS. How would you fix it?

Hold violations usually come from clock skew or very short data paths. Insert delay buffers on the data path (preferably near the endpoint), reduce skew where possible, and check that fixes don't break setup on the same paths. Fix hold at the worst hold corner (fast process, low temperature, high voltage).

VLS-367 · How would you close setup timing on a critical path with 200 ps negative slack?

Restructure logic to reduce levels, upsize or use lower-Vt cells on the critical path, improve placement to shorten wires, use useful skew, pipeline the path or relax constraints if a multicycle path is valid.

VLS-368 · How do you set up constraints for a source-synchronous interface?

Define the forwarded clock as a generated clock at the output pin, constrain output data relative to it with set_output_delay, and similarly use input delays relative to the incoming clock for receive paths, accounting for board skew.

VLS-369 · How does MCMM analysis help timing closure?

It analyses multiple modes (functional, test, low-power) and corners (process, voltage, temperature) together, so fixes for one scenario don't break another.

VLS-370 · How do you handle timing exceptions safely?

Document every false path and multicycle path with design justification, verify them with formal tools or reviews, and avoid broad wildcard exceptions that can hide real paths.

VLS-371 · How is timing analysed in a latch-based design?

STA allows time borrowing: data arriving after the latch opens but before it closes borrows time from the next stage. The tool checks setup against the closing edge, tracks how much is borrowed through each latch, and ensures the borrowed time is paid back within the pipeline loop so no stage exceeds the clock period overall.

VLS-372 · How does SI-aware STA differ from basic STA?

Basic STA ignores coupling between neighbouring wires. SI-aware STA uses extracted coupling capacitance and the timing windows of aggressor nets to add crosstalk delay (slower or faster victim transitions) and check glitch noise, so paths that pass in basic STA can fail once neighbours switching at the same time are considered.

VLS-373 · How do you fix a max-transition violation on a long, heavily loaded net?

Insert buffers to split the wire and load, upsize the driving cell, reduce fanout by cloning the driver, or move cells closer together to shorten the route. Slow transitions also increase delay, short-circuit power and noise sensitivity, so these violations matter beyond the rule itself.

VLS-374 · How do you choose clock uncertainty values during implementation?

Before CTS, uncertainty covers jitter, estimated skew and modelling margin, so it is set larger; after CTS the real skew is computed, so uncertainty is reduced to jitter plus margin. Hold uncertainty and setup uncertainty are set separately, and values come from PLL specs and flow experience.

VLS-375 · How do you validate an SDC constraint file?

Run constraint lint checks for unconstrained endpoints, missing or overlapping clocks, unclocked registers and conflicting exceptions; review that clock relationships match the architecture; and confirm exceptions with designers or formal timing-exception verification. Wrong constraints make signoff results meaningless.

Logic Synthesis

VLS-376 · Synthesis meets timing but the design fails badly after placement. Why, and what would you change?

Wire-load or simple estimates underestimated real wire delays and congestion. Use physical-aware synthesis with floorplan information (DEF), realistic constraints and margins, and check that synthesis didn't over-use high-fanout or low-Vt cells that placement can't support.

VLS-377 · How would you reduce area in a synthesised block by 15% without hurting timing?

Remove redundant logic (constant propagation, unused registers), enable resource sharing for non-critical arithmetic, use high-Vt cells where slack allows, apply multi-bit flip-flops, relax over-constrained paths and review RTL for duplicated functions. Rerun with area recovery after timing optimisation.

VLS-378 · How do you synthesise a design with multiple clock domains correctly?

Define all clocks and their relationships in SDC, declare asynchronous groups for unrelated clocks, preserve synchroniser flops (dont_touch), and avoid optimising across domain boundaries.

VLS-379 · LEC fails after synthesis. How would you debug it?

Check whether failing points are due to synthesis transformations (retiming, register merging, clock gating) not communicated to LEC, setup issues (black boxes, constants, naming), or genuine functional bugs from RTL constructs. Use guidance files and analyse non-equivalent points.

VLS-380 · How do you prevent synthesis from removing debug logic?

Use dont_touch or keep attributes, connect debug signals to observable outputs or scan chains, and avoid constant-driven logic that synthesis legitimately prunes.

VLS-381 · How do you decide between flat and hierarchical synthesis for a large SoC?

Hierarchical synthesis speeds runs and supports team-based design and reuse, but needs good budgets and interface constraints; flat synthesis optimises across boundaries for better QoR at the cost of runtime and memory.

VLS-382 · How do you handle high-fanout nets such as reset during synthesis?

Leave them unbuffered in synthesis (ideal network) and let physical design build buffer trees, or set max fanout limits and use synchronised reset distribution with timing exceptions where appropriate.

VLS-383 · How would you use retiming to improve timing?

Move registers across combinational logic to balance pipeline stages, ensuring functional equivalence and preserving reset values. Check that verification and debug visibility remain acceptable.

VLS-384 · How do you analyse and reduce power during synthesis?

Use switching activity (SAIF or VCD) to guide clock gating, operand isolation, multi-Vt mapping and low-power cell selection, then report power by hierarchy.

VLS-385 · How do you handle DesignWare or IP components in synthesis?

Use vendor libraries for optimised arithmetic and memories, set appropriate implementation choices for speed or area, and ensure licensing and constraints are applied correctly.

Physical Design (Floorplan, Placement, CTS, Routing, Signoff)

VLS-386 · How would you floorplan a block with large memories and high congestion?

Place macros at the edges with pins facing the core logic, leave channels for routing, keep data flow short between related macros and logic, add placement blockages near macro corners, and create a power grid that serves macros evenly. Iterate using congestion maps from early placement.

VLS-387 · How do you fix routing congestion hotspots?

Spread cells with density screens or partial blockages, move or reorient macros, reduce pin density through cell padding, change the floorplan, adjust layer usage or pin assignments, and resynthesise logic that creates high-fanout cones.

VLS-388 · How would you build a clock tree with low skew and low power?

Set skew and latency targets, use clock-specific buffers and inverters, route clocks on upper layers with non-default rules (double width and spacing), cluster sinks sensibly, and consider multi-source CTS or mesh for high-frequency designs. Clock gating near the root and useful skew save power and timing.

VLS-389 · IR drop analysis shows 12% dynamic drop in one region. What would you do?

Strengthen the power grid locally (more straps, wider wires, more vias), add decap cells near high-activity logic, spread high-switching cells apart, stagger clock gating to reduce simultaneous switching, and re-run timing with IR-aware delays to check the impact.

VLS-390 · How do you fix electromigration violations on power and signal nets?

Widen wires or use parallel routes and more vias to lower current density, reduce driver strength where it causes excessive current, and spread load on high-current power straps. Analyse at the correct temperature and lifetime requirements.

VLS-391 · How do you approach DRC closure on a complex block?

Fix systematic violations at their source (routing rules, cell placement, macro halos), use automated DRC repair, avoid narrow channels near macros, and run signoff DRC early on partial layouts to catch problems.

VLS-392 · How would you debug an LVS mismatch?

Check for shorts and opens in layout, mismatched device parameters, missing well or substrate ties, wrong pin labels or power connections, and compare netlist hierarchy. LVS reports point to mismatched nets or devices to trace.

VLS-393 · How do you handle antenna violations during routing?

Insert jumpers to higher metal layers, add antenna diodes near gates, or reroute to break long metal segments connected to gates before the top layer.

VLS-394 · How do you plan power grid for a multi-voltage design?

Create separate grids for each domain, place power switches for gated domains, ensure level shifters and isolation cells are powered correctly, and verify IR drop for each domain.

VLS-395 · What checks are needed at signoff before tapeout?

STA at all corners and modes, IR drop and EM, DRC, LVS, antenna, LEC, power and thermal checks, and DFT checks, with all violations closed or waived.

Low-Power Design

VLS-396 · How would you cut the dynamic power of a mobile SoC by 30%?

Combine DVFS for performance states, aggressive clock gating at architectural and RTL levels, power gating for idle blocks, lower-activity data encoding, memory power modes and optimised software scheduling. Measure with realistic activity to find the largest consumers.

VLS-397 · How do you design a power-gating scheme for a CPU core?

Use header or footer switches sized for IR drop and wake-up time, isolation cells on outputs, retention flops for critical state, a power management controller sequencing power-down and power-up, and staged switch turn-on to limit in-rush current.

VLS-398 · How do you choose which registers need retention?

Retain only the state needed to resume quickly (architectural registers, configuration); restore the rest by reset or software. Retention flops cost area and leakage, so minimise them.

VLS-399 · How do you verify that isolation cells are placed correctly?

Use UPF-aware static checks for missing or redundant isolation, ensure isolation enable is active before power-down, and run power-aware simulations of power sequences.

VLS-400 · How would you implement DVFS on a chip?

Define operating points of voltage and frequency, use a PMIC or on-chip regulator, change frequency before lowering voltage (and raise voltage before increasing frequency), and characterise timing at each point.

VLS-401 · How would you reduce leakage in an always-on domain?

Use high-Vt cells and long-channel devices where speed allows, keep the domain as small as possible, lower its supply voltage, use body bias where available, and turn off unused memories or put them in retention mode.

VLS-402 · How do you estimate the power savings of clock gating before RTL changes?

Collect switching activity from representative workloads, find register banks whose enables are frequently inactive, and estimate clock tree and register power saved with power analysis tools. Gate only groups large enough to outweigh the ICG overhead.

VLS-403 · How do you handle level shifting between a 0.8 V core and 1.2 V I/O domain?

Insert low-to-high level shifters (which need both supplies) on signals going up, high-to-low shifters going down, place them at domain boundaries per UPF, and verify timing and power-down behaviour with isolation where domains can be off.

VLS-404 · How would you design a low-power wake-up path for an IoT chip?

Keep an always-on domain with a low-frequency RTC oscillator and wake-up logic, power-gate everything else, restore state from retention or memory, and sequence clocks and power so the chip wakes quickly without in-rush problems.

VLS-405 · How do you validate power estimates against silicon?

Measure current at different modes and workloads on test chips, compare with pre-silicon estimates using the same activity, and refine models (library characterisation, activity factors, IR effects).

Design for Testability

VLS-406 · Fault coverage is stuck at 92%. How would you raise it toward 99%?

Analyse untestable and undetected faults: add test points to improve controllability and observability, fix DFT rule violations (uncontrollable clocks, asynchronous resets, black boxes), wrap memories and analog blocks, and run ATPG with more patterns or sequential capture.

VLS-407 · How would you test a design with several clock domains using scan?

Use a test clock controller (OCC) to provide controllable capture pulses per domain, add lockup latches between chains crossing domains, and generate patterns that capture domains separately or with defined relationships.

VLS-408 · How do you reduce test time and data volume for a large SoC?

Use scan compression (EDT), more parallel scan chains, hierarchical DFT with core wrappers and pattern reuse, and multi-site testing on the tester.

VLS-409 · How do you test embedded memories?

Insert MBIST controllers running March algorithms, add repair logic with redundant rows/columns and fuse programming, and test retention and data patterns.

VLS-410 · How do you test at-speed transition faults?

Use launch-on-capture or launch-on-shift patterns with on-chip clock control providing two fast pulses, and constrain timing for at-speed paths.

VLS-411 · How would you diagnose a scan chain that fails on silicon?

Use chain integrity tests to locate the failing segment, apply diagnostic patterns, check for hold violations or clock issues, and use physical failure analysis if needed.

VLS-412 · How do you make an analog block such as a PLL or ADC testable in production?

Add an analog test bus to route key internal nodes to pins, loopback paths (DAC to ADC, TX to RX), and built-in self-test that measures lock, frequency or code histograms digitally. Digital observation keeps tester cost down compared with full analog measurement on expensive instruments.

VLS-413 · How do you get high test coverage in a design with power-gated domains?

Define test modes where each domain is powered and testable, include isolation, retention and power-switch logic in the scan structure, add tests that exercise power-down and wake-up sequences, and make sure ATPG understands which domains are on during each pattern.

VLS-414 · How do you use boundary scan to test board-level connections?

JTAG boundary-scan cells at each I/O let a tester drive values onto pins of one chip and capture them at connected chips (EXTEST), detecting opens and shorts on board traces without physical probes. BSDL files describe each chip's scan cells for the test software.

VLS-415 · How does adding DFT affect timing and area, and how do you limit the impact?

Scan muxes add delay on flop inputs and wiring for scan chains, and compression and MBIST add area (often a few percent). Order scan chains by placement to cut wire length, use scan flops with low overhead, and include DFT logic in timing closure from the start.

FPGA, Analog/Mixed-Signal & Fabrication

VLS-416 · An FPGA design fails timing at 250 MHz. What would you try?

Check critical paths in the timing report, add pipeline registers, use DSP and block RAM output registers, reduce logic levels, avoid long carry chains, apply floorplanning (Pblocks) for related logic, replicate high-fanout registers, and try different synthesis and implementation strategies.

VLS-417 · How would you choose between an FPGA and an ASIC for a product?

FPGAs have no NRE and fast time to market and can be updated, but cost more per unit and use more power. ASICs need high NRE and long development but give the lowest unit cost, power and highest performance at volume. Compare volume, power budget, schedule and flexibility needs.

VLS-418 · How do you design a PLL loop filter for stability and low jitter?

Choose loop bandwidth (often about one-tenth of the reference frequency or less) to balance reference noise and VCO noise, set phase margin around 50–60° with the charge pump current and RC filter values, and simulate jitter and lock time.

VLS-419 · How do you lay out an analog differential pair for good matching?

Use common-centroid or interdigitated layouts, identical orientation and surroundings, dummy devices at edges, symmetrical routing, and keep devices away from stress sources and well edges.

VLS-420 · How would you integrate a sensitive ADC into a noisy digital SoC?

Separate analog and digital power domains, use guard rings and deep N-well isolation, careful substrate and ground planning, filtering and decoupling, and avoid routing digital lines near analog inputs.

VLS-421 · How do you estimate wafer cost per good die?

Cost per good die = wafer cost/(dies per wafer × yield). Dies per wafer depends on die area and edge loss; yield depends on defect density (e.g. Poisson or Murphy model) and die area.

VLS-422 · How do you handle process variation in analog design?

Run Monte Carlo and corner simulations, design with margin, use calibration and trimming, and choose topologies that are less sensitive to mismatch.

VLS-423 · How would you migrate a design from one technology node to another?

Re-characterise standard cells and memories, re-synthesise and re-run physical design with new rules, redesign analog blocks, verify timing and power, and update DFT and packaging.

VLS-424 · How does chiplet-based design change the VLSI flow?

It requires die-to-die interfaces (e.g. UCIe), advanced packaging (2.5D/3D), system-level partitioning, thermal and power co-design, and known-good-die testing.

VLS-425 · How do you improve yield in a new process?

Analyse defect data and failure modes, use DFM rules (wire spreading, via doubling), add redundancy in memories, and collaborate with the foundry to fix systematic issues.

Other levels: Basic · Intermediate · Tricky · All Electronics / VLSI questions