Verilog HDL

Full Verilog course — 27 topics from the basics to advanced use.

Lessons

• Writing Testbenches
• Self-Checking Testbenches
• Tasks & Functions
• Simulation Time, Events & Races
• Synthesis: From Verilog to Gates
• Common Pitfalls & Lint
• FPGA & ASIC Design Flow
• RTL Coding Guidelines
• Project: UART Transmitter
• Project: Synchronous FIFO
• Project: PWM Generator
• What Is Verilog?
• Your First Module & Testbench
• Values, Literals & Vectors
• Nets vs Variables: wire and reg
• Operators & Expression Width
• Structural, Dataflow & Behavioral Modeling
• always @(*), if & case — and Accidental Latches
• Decoders, Encoders & casez
• Adders & Arithmetic Hardware
• Hierarchy, Parameters & generate
• Flip-Flops, Clocks & Resets
• Blocking vs Non-Blocking Assignment
• Registers, Counters & LFSRs
• Finite State Machines (Moore & Mealy)
• Memories: RAM & ROM
• Clock Domains, Synchronizers & Edge Detection