What Is Verilog?

A language for describing hardware: circuits that all run at the same time, not instructions that run one after another.

Verilog is a hardware description language (HDL). A C or Python program is a list of steps a processor executes one at a time. A Verilog description is a circuit: gates, flip-flops and wires that all work in parallel, all the time. The same text is used for two different jobs: simulating the circuit on a computer to check it, and synthesizing it into real hardware on an FPGA or a chip.

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// expecting a to be computed first, then used assign y = a & c; assign a = b | d;

// order does not matter: both are wires that always // reflect their inputs assign a = b | d; assign y = a & c;

These are two pieces of hardware connected by the wire a, not two steps. Swapping the lines describes exactly the same circuit.

always @(posedge clk) q <= d; // timing comes from the clock

Delays are ignored by synthesis. Real hardware timing comes from clocks and from the physical delay of the cells, not from # in the code.

What is the difference between simulation and synthesis?

Simulation executes the Verilog on a computer (with a testbench) to see how the circuit behaves over time. Synthesis converts the synthesizable part of the description into a netlist of real hardware cells (gates and flip-flops, or FPGA look-up tables).

Register-transfer level: describing a design as registers (flip-flops) and the combinational logic that computes the values transferred between them on each clock edge. It is the level at which Verilog designs are normally written.

Name two things that are valid Verilog but cannot be synthesized.

Delays such as #10, and system tasks such as $display or $finish (also initial blocks in most ASIC flows, file I/O, and real-number arithmetic).