Nets vs Variables: wire and reg

wire connects things, reg holds values assigned in procedures — and neither one means 'register'.

The two data types every Verilog beginner meets are wire and reg, and their names are misleading. A wire (a net) is a connection: it carries whatever drives it. A reg is a variable: it keeps the last value assigned to it inside an initial or always block. A reg becomes a flip-flop only if it is assigned on a clock edge; in combinational code it becomes plain gates.

Other types you will meet

output y; always @(*) y = a & b; // error: y is a wire output reg y; always @(*) y = a & b;

A signal assigned in an always block must be a variable (reg). A plain output is a wire.

reg [7:0] total; assign total = a + b; // error wire [7:0] total; assign total = a + b;

assign drives nets. A reg can only be assigned in procedural blocks.

Does declaring a signal as reg create a flip-flop?

No. reg only means it is assigned in a procedural block. It becomes a flip-flop if it is assigned on a clock edge (always @(posedge clk)); in an always @(*) block it becomes combinational logic.

What value does a wire have when two drivers drive 0 and 1?

x: the conflict cannot be resolved. In real hardware this is a short circuit (bus contention).