RTL Coding Guidelines

Naming, reset strategy, file organization and the conventions reviewers expect in professional Verilog.

Professional RTL is written for two readers: the synthesis tool and the next engineer. Teams follow coding guidelines so that designs are predictable, reviewable and reusable. These are the conventions you will meet in most companies.

Design rules

assign gated_clk = clk & enable; always @(posedge gated_clk) ...

always @(posedge clk) if (enable) ...

Gating a clock with logic creates glitches and skew. Use a clock enable (or the vendor's clock-gating cell in ASICs, inserted by the tools).

Why is resetting data-path registers often skipped?

Their values are overwritten before use and qualified by a valid flag, so resetting them adds routing and area without changing behaviour. Control registers (state, counters, valid bits) must be reset.

Why register module outputs?

It isolates timing: the next module's input path starts at a flip-flop, so long combinational paths cannot chain across module boundaries, and timing closure becomes local.