Short-Channel & Advanced MOSFET Effects

What breaks when MOSFETs shrink. Learn charge sharing and threshold roll-off, drain-induced barrier lowering (DIBL), punch-through, velocity saturation and its effect on drive current, channel-length modulation, mobility degradation, hot-carrier effects and injection, gate-oxide tunnelling and breakdown, gate-induced drain leakage (GIDL), subthreshold leakage and its temperature dependence, narrow-width effects, self-heating, and the countermeasures (halo/pocket implants, LDD, retrograde wells, strain, high-k metal gate, thin bodies) — with Python quantifying velocity saturation vs length, DIBL-driven leakage and V_T-leakage trade-offs.

When the channel length approaches the depletion widths of the source and drain junctions, the gate no longer controls the channel alone: the drain reaches in, lowering the barrier. Threshold becomes length- and drain-voltage-dependent, and leakage rises.

At the same time, very high lateral fields saturate carrier velocity and create hot carriers. Every modern transistor architecture exists to fight these effects.

An analogy

A long MOSFET is like a canal lock gate controlled by one keeper (the gate). In a very short canal, the downstream water level (drain) pushes on the gate too — the keeper loses control and water leaks through even when the gate is 'closed'.

Electrostatic effects

Symptoms of lost gate control:

Transport effects

Velocity saturation limits drive current and makes g_m nearly independent of overdrive. Mobility degradation from high vertical fields (thin oxides, high doping) reduces µ_eff. Strain engineering (SiGe S/D for PMOS, stress liners for NMOS) and high-mobility channels partly restore performance. Near-ballistic transport and source-injection velocity become the relevant limits at the smallest lengths.

Hot carriers and oxide effects

Carriers accelerated near the drain gain enough energy to create interface traps or be injected into the oxide (hot-carrier degradation, HCI), shifting V_T and reducing g_m over time — lightly doped drains (LDD) spread the field. Thin oxides leak by direct tunnelling (gate leakage), solved by high-k dielectrics with thicker physical thickness. High drain-gate fields cause band-to-band tunnelling at the drain (GIDL), important in DRAM and low-leakage designs.

Engineering countermeasures

Halo/pocket implants suppress roll-off and punch-through, shallow extension junctions reduce charge sharing, retrograde wells limit surface doping, high-k metal gates raise C_ox without leakage, and finally thin-body architectures (FD-SOI, FinFET, GAA) put the gate around a thin channel so λ_n shrinks. Self-heating in these confined structures (poor thermal conductivity of oxides) then becomes a new reliability concern.

Formulas

Worked example: Critical field

Given: µ 300 cm²/V·s, v_sat 10⁷ cm/s

Find: E_c.

Answer: 6.7 × 10⁴ V/cm (0.67 V across 100 nm)

Worked example: DIBL

Given: V_T 0.40 V at V_DS 0.05 V, 0.33 V at 1.0 V

Find: DIBL.

Answer: ≈ 74 mV/V

Worked example: Saturated current

Given: W 1 µm, C_ox 2.9 µF/cm², v_sat 10⁷, V_ov 0.5 V

Find: Short-channel limit I_D.

Answer: 1.45 mA/µm

Drain influence in short channels

  Long channel:  source barrier set by gate only      ─┐____________┌─  (flat barrier)
  Short channel: drain field lowers the source barrier ─┐__╲_________   (DIBL)
                 source/drain depletions share charge → lower V_T (roll-off)
                 extreme: depletions touch below the surface → punch-through leakage
  Counter: halo/pocket implants, thinner oxide, shallow junctions, thin bodies (SOI/FinFET/GAA)

Charge sharing means part of the depletion charge under the gate is supported by the source/drain junctions instead of the gate, so less gate voltage is needed to invert — threshold falls with shorter L and higher V_DS. The electrostatic scale length λ_n tells how quickly the drain's influence decays: gate lengths need to be several λ_n.

Velocity saturation, DIBL and leakage

import math
# Short-channel effects: velocity saturation, DIBL leakage, Vt roll-off and subthreshold leakage
eps_ox = 3.9 * 8.854e-14
tox = 1.2e-7                                    # 1.2 nm EOT
Cox = eps_ox / tox
W, Vov, mu, vsat = 1e-4, 0.5, 250.0, 1e7        # 1 um width
for L_nm in (1000, 100, 30):
    L = L_nm * 1e-7
    Ec = 2 * vsat / mu
    Id_long = 0.5 * mu * Cox * W / L * Vov**2
    Id_vs = W * Cox * vsat * Vov**2 / (Vov + Ec * L)     # velocity-saturation model
    print(f"L = {L_nm:4d} nm: square law {Id_long*1e3:8.3f} mA, with vsat {Id_vs*1e3:6.3f} mA (ratio {Id_vs/Id_long:.2f})")
S = 0.085                                       # 85 mV/dec
for dibl_mV_V, VDD in ((20, 1.0), (100, 1.0)):
    dVt = dibl_mV_V * 1e-3 * VDD
    print(f"DIBL {dibl_mV_V} mV/V at VDD {VDD} V: Vt drops {dVt*1e3:.0f} mV -> off-current x{10**(dVt/S):.1f}")
for Vt in (0.45, 0.35, 0.25):
    Ioff = 100e-9 * 10 ** (-Vt / S)             # 100 nA/um at VGS = 0 for Vt = 0
    print(f"Vt = {Vt:.2f} V: Ioff ~ {Ioff*1e12:.2f} pA/um -> 1e9 transistors x 1 um: {Ioff*1e9:.3f} A")
# L = 1000 nm: square law    0.090 mA, with vsat  0.085 mA (ratio 0.94)
# L =  100 nm: square law    0.899 mA, with vsat  0.553 mA (ratio 0.62)
# L =   30 nm: square law    2.997 mA, with vsat  0.972 mA (ratio 0.32)
# DIBL 20 mV/V at VDD 1.0 V: Vt drops 20 mV -> off-current x1.7
# DIBL 100 mV/V at VDD 1.0 V: Vt drops 100 mV -> off-current x15.0
# Vt = 0.45 V: Ioff ~ 0.51 pA/um -> 1e9 transistors x 1 um: 0.001 A
# Vt = 0.35 V: Ioff ~ 7.63 pA/um -> 1e9 transistors x 1 um: 0.008 A
# Vt = 0.25 V: Ioff ~ 114.50 pA/um -> 1e9 transistors x 1 um: 0.115 A

At L = 1 µm the square law holds; at 30 nm velocity saturation cuts drive current to a third of the square-law prediction, and current grows only linearly with overdrive. A DIBL of 100 mV/V raises off-current 15× at V_DD = 1 V. Lowering V_T from 0.45 to 0.25 V (to recover speed at low V_DD) multiplies leakage >200× — the central power/performance trade-off of CMOS scaling.

Common mistakes

Applications

Key takeaways

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