MOSFET Capacitances, Gate Charge & Switching

How fast a MOSFET really switches. Learn intrinsic and parasitic capacitances (C_gs, C_gd, C_ds, C_db, overlap), datasheet C_iss, C_oss, C_rss and their voltage dependence, the gate-charge curve (Q_g(th), Q_gs, Q_gd, Q_g) and the Miller plateau, the four switching intervals at turn-on and turn-off, gate-driver requirements (current, voltage, resistance, Kelvin source), switching, conduction, C_oss and gate-drive losses, dv/dt and di/dt, parasitic inductance, ringing and false turn-on — with Python computing plateau times, switching energies, C_oss loss, gate-drive power and dv/dt for a 400 V, 10 A hard-switched MOSFET.

A MOSFET gate is a capacitor network. Switching means charging and discharging it through a gate driver; the drain voltage and current transition while the gate sits on the Miller plateau. The time spent there sets switching loss.

Datasheet gate-charge figures turn this into simple arithmetic: time = charge ÷ gate current.

An analogy

Switching a MOSFET is like pushing open a heavy door with a spring on the other side (the Miller capacitance): you push steadily (gate current), but while the door is moving (drain voltage changing) all your effort goes into fighting that spring, so the handle (gate voltage) stays still — the plateau.

Capacitances

Where they come from:

Loss mechanisms

Conduction (I²R_DS(on), R_DS(on) rises ~1.5–2× from 25 to 125 °C), switching overlap (∝ V·I·t·f), C_oss energy dumped at hard turn-on, body-diode conduction during dead time and its reverse recovery (Q_rr), and gate-drive power. Soft-switching topologies (ZVS, ZCS) eliminate overlap and C_oss losses, allowing higher frequencies.

Gate driving

Choose drive voltage for the R_DS(on) spec (4.5 V logic-level, 10–12 V standard, 15–18 V/−3…−5 V for SiC). Peak current = ΔV/R_g; separate turn-on and turn-off resistors tune dv/dt. Use a Kelvin-source connection so di/dt across source inductance doesn't subtract from V_GS; negative turn-off or Miller clamps prevent C_gd-induced false turn-on in bridges.

Parasitics and ringing

Package and PCB inductance in the power loop resonates with C_oss, causing overshoot (V = L·di/dt) and ringing that raise EMI and voltage stress; gate-loop inductance can make the gate oscillate. Minimise loop areas, use low-inductance packages (TOLL, LFPAK, DirectFET, Kelvin TO-247-4), snubbers and ferrite beads where needed.

Formulas

Worked example: Plateau time

Given: Q_gd 20 nC, I_g 1 A

Find: t.

Answer: 20 ns

Worked example: Conduction loss

Given: I_rms 15 A, R_DS(on) 8 mΩ at 25 °C, ×1.6 hot

Find: P.

Answer: 2.9 W

Worked example: Miller spike

Given: C_gd 20 pF, dv/dt 50 V/ns, R_g,off 2 Ω

Find: Induced V_GS.

Answer: 2 V (close to V_th!)

Gate-charge curve and switching intervals

  V_GS
  12 ┤                                    ___ ── (charging C_iss at full V_DS low)
   5 ┤          ┌──────── Miller plateau ─┘   ← V_DS falls here (Q_gd)
   3 ┤ V_th ───╱ ← I_D rises here (Q_gs above V_th)
   0 ┼────────╱────────┬──────────────┬─────────── Q_g (nC)
     0       Q_th     Q_gs = 10     Q_gs+Q_gd = 25          Q_g = 40

Turn-on: (1) charge to V_th — nothing happens; (2) current rises from 0 to I_D while V_DS stays at the bus; (3) plateau — V_DS falls as C_gd discharges; (4) gate charges to V_drv, R_DS(on) reaches its final value. Turn-off runs in reverse. Intervals 2 and 3 are where V × I losses occur.

Switching times and losses from gate charge

# Power-MOSFET switching from gate charge: Miller plateau time, losses, gate-drive power, Coss loss
Vdrv, Vpl, Vth, Rg = 12.0, 5.0, 3.0, 5.0            # driver, Miller plateau, threshold, total gate R
Qgs, Qgd, Qg = 10e-9, 15e-9, 40e-9
Vbus, I, f = 400.0, 10.0, 100e3
Ig_on = (Vdrv - Vpl) / Rg
Ig_off = Vpl / Rg
Q_th_to_pl = Qgs - 5e-9                             # gate charge between Vth and the plateau (5 nC below Vth)
t_rise_i = Q_th_to_pl / ((Vdrv - (Vth + Vpl) / 2) / Rg)
t_fall_i = Q_th_to_pl / (((Vth + Vpl) / 2) / Rg)
t_on = Qgd / Ig_on
t_off = Qgd / Ig_off
print(f"gate current on {Ig_on:.2f} A / off {Ig_off:.2f} A")
print(f"turn-on: current rise {t_rise_i*1e9:.1f} ns, voltage fall {t_on*1e9:.1f} ns; turn-off: voltage rise {t_off*1e9:.1f} ns, current fall {t_fall_i*1e9:.1f} ns")
E_on = 0.5 * Vbus * I * (t_rise_i + t_on)
E_off = 0.5 * Vbus * I * (t_off + t_fall_i)
print(f"switching energy on {E_on*1e6:.1f} uJ, off {E_off*1e6:.1f} uJ -> {(E_on+E_off)*f:.1f} W at 100 kHz")
Coss_eq = 100e-12
print(f"Coss energy 0.5*Coss*V^2 = {0.5*Coss_eq*Vbus**2*1e6:.1f} uJ -> {0.5*Coss_eq*Vbus**2*f:.2f} W (hard switching)")
print(f"gate-drive power Qg*Vdrv*f = {Qg*Vdrv*f*1e3:.0f} mW; dv/dt at turn-off = {Vbus/t_off/1e9:.1f} V/ns")
# gate current on 1.40 A / off 1.00 A
# turn-on: current rise 3.1 ns, voltage fall 10.7 ns; turn-off: voltage rise 15.0 ns, current fall 6.2 ns
# switching energy on 27.7 uJ, off 42.5 uJ -> 7.0 W at 100 kHz
# Coss energy 0.5*Coss*V^2 = 8.0 uJ -> 0.80 W (hard switching)
# gate-drive power Qg*Vdrv*f = 48 mW; dv/dt at turn-off = 26.7 V/ns

With a 12 V driver and 5 Ω total gate resistance, the plateau lasts 11 ns at turn-on and 15 ns at turn-off (less gate current is available: only V_pl/R_g). At 400 V/10 A and 100 kHz the resulting switching loss is ~7 W, plus 0.8 W for charging C_oss — far more than the 48 mW gate-drive power. The 27 V/ns turn-off dv/dt stresses layout and gate drive (Miller-induced turn-on).

Common mistakes

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Key takeaways

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