MOS Devices, CMOS & Advanced Transistors

MOS Devices, CMOS & Advanced Transistors: The MOS Capacitor: Accumulation, Depletion, Inversion & C–V, MOSFET Operation: Threshold, Regions, Body Effect & Subthreshold, MOSFET Capacitances, Gate Charge & Switching, Short-Channel & Advanced MOSFET Effects, CMOS Devices: Inverter, Power, Delay & Scaling, FinFET, Gate-All-Around & SOI Transistors.

• The MOS Capacitor: Accumulation, Depletion, Inversion & C–V — The foundation of every MOSFET. Learn the metal–oxide–semiconductor structure, oxide capacitance, work-function difference φ_ms, flat-band voltage and oxide charges (fixed, mobile, trapped, interface traps), the band diagrams and charge distributions in accumulation, depletion, weak and strong inversion, surface potential and the 2φ_F inversion criterion, maximum depletion width, threshold voltage V_T = V_FB + 2φ_F + Q_d/C_ox, high- and low-frequency C–V curves, deep depletion, and extracting oxide thickness, doping, V_FB and interface-trap density from C–V — with Python computing C_ox, φ_F, V_FB, W_max, V_T and normalised C–V values.
• MOSFET Operation: Threshold, Regions, Body Effect & Subthreshold — From MOS capacitor to transistor. Learn MOSFET structure (gate stack, source, drain, body, channel), NMOS/PMOS, enhancement and depletion devices, channel formation and inversion charge Q_inv = C_ox(V_GS − V_T), gradual-channel derivation of the triode and saturation equations, pinch-off, channel-length modulation, body effect, subthreshold (weak-inversion) conduction and swing S, mobility degradation with vertical field, temperature effects on V_T and mobility (ZTC point), output/transfer characteristics, R_DS(on), g_m and r_o, leakage components, and why MOSFET 'saturation' differs from BJT saturation — with Python computing drain currents, body-effect thresholds, subthreshold swing and I_on/I_off.
• MOSFET Capacitances, Gate Charge & Switching — How fast a MOSFET really switches. Learn intrinsic and parasitic capacitances (C_gs, C_gd, C_ds, C_db, overlap), datasheet C_iss, C_oss, C_rss and their voltage dependence, the gate-charge curve (Q_g(th), Q_gs, Q_gd, Q_g) and the Miller plateau, the four switching intervals at turn-on and turn-off, gate-driver requirements (current, voltage, resistance, Kelvin source), switching, conduction, C_oss and gate-drive losses, dv/dt and di/dt, parasitic inductance, ringing and false turn-on — with Python computing plateau times, switching energies, C_oss loss, gate-drive power and dv/dt for a 400 V, 10 A hard-switched MOSFET.
• Short-Channel & Advanced MOSFET Effects — What breaks when MOSFETs shrink. Learn charge sharing and threshold roll-off, drain-induced barrier lowering (DIBL), punch-through, velocity saturation and its effect on drive current, channel-length modulation, mobility degradation, hot-carrier effects and injection, gate-oxide tunnelling and breakdown, gate-induced drain leakage (GIDL), subthreshold leakage and its temperature dependence, narrow-width effects, self-heating, and the countermeasures (halo/pocket implants, LDD, retrograde wells, strain, high-k metal gate, thin bodies) — with Python quantifying velocity saturation vs length, DIBL-driven leakage and V_T-leakage trade-offs.
• CMOS Devices: Inverter, Power, Delay & Scaling — Complementary MOS from the device viewpoint. Learn the CMOS inverter (NMOS pull-down, PMOS pull-up), voltage transfer characteristic and its regions, switching threshold and sizing, noise margins, static/dynamic/short-circuit/leakage power (P = αCV²f), propagation delay and fan-out, NAND/NOR/transmission gates, latch-up in bulk CMOS, and scaling — Dennard scaling and its end, Moore's law context, feature size and 'node' names, interconnect delay, EUV and design-technology co-optimisation — with Python computing switching thresholds, dynamic and leakage power, delay and Dennard scaling factors, and a solved VTC.
• FinFET, Gate-All-Around & SOI Transistors — Modern transistor architectures. Learn why planar bulk MOSFETs ran out of electrostatic control, the natural length λ and how multiple gates shrink it, fully-depleted SOI (FD-SOI) and partially-depleted SOI with back-gate biasing, FinFET/tri-gate structure (fin height, width, pitch, quantised width), GAA nanosheets and nanowires (stacked sheets, variable width, forksheet and CFET concepts), advantages (subthreshold swing, DIBL, variability, leakage) and limitations (parasitic capacitance/resistance, self-heating, process complexity), SOI for RF and radiation-hard applications — with Python comparing natural lengths and effective widths for planar, FinFET and GAA devices.