Packaging, Advanced Packaging & Thermal Path

From die to component. Learn die attach, lead frames, wire bonding vs flip-chip, package families (SOT, SOIC, QFP, QFN, BGA, TO/D²PAK power packages, ceramic packages, wafer-level and chip-scale packages), package parasitics (bond-wire inductance, ground bounce), thermal paths and θ_JA/θ_JC/Ψ_JT, moisture sensitivity, and advanced packaging: multi-chip modules, SiP, 2.5D interposers, 3D ICs with TSVs, hybrid bonding, chiplets and high-bandwidth interconnect (HBM, UCIe), thermal challenges of stacking, and power-module packaging (DBC, sintered silver, double-sided cooling) — with Python comparing junction temperatures across packages, bond-wire vs flip-chip inductance and TSV capacitance.

A package protects the die, connects it electrically to the board, removes its heat and survives years of thermal cycling. For many products the package limits performance: its inductance limits speed, its thermal resistance limits power, and its interconnect density limits bandwidth.

Advanced packaging — chiplets, interposers, 3D stacking — has become as important as transistor scaling for system performance.

An analogy

A package is the die's house: walls (moulding compound) protect it, doors and corridors (bond wires, bumps) connect it to the street (PCB), and the roof and chimney (heat spreader, exposed pad) let heat out. Advanced packaging builds apartment blocks where many dies live close together.

Package families

Common packages:

Assembly and reliability

Die attach (epoxy, solder, sintered silver), wire bonding (Au, Cu, Al wedge for power), moulding, and board assembly. Moisture absorbed by plastic packages can crack them during reflow ('popcorning') — MSL ratings define floor life and baking. Thermal cycling fatigues solder joints and wire bonds (CTE mismatch); power cycling lifts bond wires in power modules. Qualification follows JEDEC/AEC standards.

Advanced packaging

Multi-chip modules and system-in-package combine several dies (RF, memory, logic, passives). 2.5D integration places chiplets side by side on a silicon interposer (or organic/bridge substrates like EMIB) with µm-scale wiring — e.g. GPUs with HBM stacks. 3D ICs stack dies connected by TSVs and micro-bumps or hybrid (Cu–Cu) bonding at < 10 µm pitch. Die-to-die standards (UCIe, BoW) enable chiplet ecosystems.

Thermal and electrical challenges

Stacked dies trap heat — hot spots and thermal coupling limit 3D logic stacking; memory-on-logic needs careful floorplanning. Package parasitics (bump/ball inductance, plane resonances) shape power-integrity and signal-integrity design. Power modules use DBC/AMB ceramic substrates, sintered-silver die attach, copper clips and double-sided cooling to handle SiC's high power density.

Formulas

Worked example: Max power

Given: T_J,max 125 °C, T_A 70 °C, θ_JA 40 °C/W

Find: P_max.

Answer: 1.375 W

Worked example: Wire inductance

Given: 2 mm wire, 20 mA/ns

Find: Bounce.

Answer: 40 mV

Worked example: Parallel bonds

Given: 4 wires of 3 nH (uncoupled)

Find: Effective L.

Answer: 0.75 nH

Wire-bond vs flip-chip cross-sections

  Wire-bond QFN                            Flip-chip BGA
     ╭─ bond wire (1–3 nH) ─╮                  die (face down)
   ▓▓▓▓ die ▓▓▓▓            │                 ● ● ● ● bumps (≈ 0.05 nH each, area array)
   ════ die attach ════     lead               ══════ substrate (build-up layers) ══════
   ████ exposed pad → PCB thermal vias          ● ● ● ● ● BGA balls → PCB
  Heat: die → attach → pad → PCB               Heat: die backside → TIM → lid/heatsink

Wire bonds connect peripheral pads with millimetre-long wires (inductance, limited I/O count). Flip-chip places solder or copper-pillar bumps across the whole die face — short, low-inductance connections and thousands of I/Os — and exposes the die backside for heat removal. QFN exposed pads send heat into PCB copper through vias.

Thermal, inductance and TSV numbers

import math
# Package thermal path, bond-wire inductance and ground bounce, TSV capacitance
P, Ta = 2.0, 50.0
for name, theta in (("SOIC-8 (thja ~120 C/W)", 120), ("QFN with exposed pad (~35 C/W)", 35), ("BGA + heatsink (~12 C/W)", 12)):
    print(f"{name:32s}: Tj = {Ta + P*theta:.0f} C at 2 W")
L_per_mm, length = 1.0e-9, 3.0
L = L_per_mm * length
didt = 0.1 / 1e-9
print(f"3 mm bond wire ~ {L*1e9:.0f} nH -> ground bounce L*di/dt = {L*didt:.1f} V for 100 mA in 1 ns; flip-chip bump ~0.05 nH -> {0.05e-9*didt*1e3:.0f} mV")
r, h, tox = 2.5e-6, 50e-6, 0.2e-6
C_tsv = 2 * math.pi * 3.9 * 8.854e-12 * h / math.log((r + tox) / r)
print(f"TSV (5 um dia, 50 um deep, 200 nm liner): C ~ {C_tsv*1e15:.0f} fF")
# SOIC-8 (thja ~120 C/W)          : Tj = 290 C at 2 W
# QFN with exposed pad (~35 C/W)  : Tj = 120 C at 2 W
# BGA + heatsink (~12 C/W)        : Tj = 74 C at 2 W
# 3 mm bond wire ~ 3 nH -> ground bounce L*di/dt = 0.3 V for 100 mA in 1 ns; flip-chip bump ~0.05 nH -> 5 mV
# TSV (5 um dia, 50 um deep, 200 nm liner): C ~ 141 fF

At 2 W, a leaded SOIC reaches an impossible 290 °C, a QFN with a soldered exposed pad 120 °C, and a BGA with heatsink 74 °C — the package determines the power a die can dissipate. A 3 mm bond wire produces 0.3 V of ground bounce for a 100 mA/ns edge; a flip-chip bump only 5 mV. A 5 µm TSV adds ~140 fF — significant for high-speed 3D signalling.

Common mistakes

Applications

Key takeaways

Going further