CMOS Process Flow, Advanced CMOS & Yield

Putting the steps together. Walk through a simplified twin-well CMOS flow — starting wafer, wells, shallow-trench isolation, gate oxide/gate stack, LDD/extension implants, spacers, source/drain implants and anneal, silicide, contacts, interconnect and passivation — then advanced CMOS: high-k/metal gate and replacement-metal-gate (gate-last), strain engineering, fin formation, GAA nanosheet release, EUV layers, backside power delivery and 3D integration; and the economics: wafer test, defect density, Poisson and Murphy yield models, dies per wafer, cost per good die and why chiplets help — with Python computing yield vs die size, cost per die and chiplet yield advantage.

A CMOS process integrates hundreds of steps so that NMOS and PMOS transistors, isolation, contacts and interconnects all work together with tight tolerances. Each step's thermal budget and ordering constrains the others.

Yield — the fraction of working dies — turns process quality into product cost. Big dies are disproportionately expensive, which drives chiplet architectures.

An analogy

A process flow is like building a skyscraper floor by floor with strict ordering: foundations (wells, isolation) before columns (gates), columns before wiring, and nothing that needs high heat can come after the plastic fittings (metals) are installed.

Key modules

Building blocks of the flow:

Advanced CMOS fabrication

FinFETs: fins patterned by self-aligned multiple patterning or EUV, STI recess sets fin height, dummy gate over fins, epitaxial raised S/D, replacement metal gate. GAA nanosheets: Si/SiGe superlattice epitaxy, fin patterning, dummy gate, inner-spacer formation, selective SiGe removal (channel release), gate wrap-around by ALD. Backside power delivery moves power rails under the transistors (wafer bonding, thinning, nano-TSVs), freeing front-side routing. 3D integration stacks dies or wafers with hybrid bonding.

Yield and test

Yield components: line yield (wafers surviving the process), die yield (random defects, systematic/design-sensitive failures, parametric yield). Wafer-level test (probe cards) screens dies; inline defect inspection and electrical test structures monitor the process. Yield learning — finding and eliminating defect sources — is the core of ramping a new node. Design for manufacturing (DFM) rules, redundancy (spare SRAM rows) and binning improve effective yield.

Thermal budget and integration

Every high-temperature step diffuses earlier dopants; process integration orders steps so that the total thermal budget meets junction requirements. High-k/metal gates, SiGe channels and 3D stacking all introduce new temperature constraints, requiring low-temperature epitaxy, laser anneals and hybrid bonding compatible with BEOL.

Formulas

Worked example: Poisson yield

Given: D₀ 0.2 cm⁻², A 1 cm²

Find: Y.

Answer: 82%

Worked example: Cost per good die

Given: $8000 wafer, 400 dies, 80% yield

Find: C.

Answer: $25

Worked example: Defect density needed

Given: Target 90% Poisson yield, 2 cm² die

Find: D₀.

Answer: 0.053 cm⁻²

Simplified twin-well CMOS flow

  p-type wafer (+ epi)
  → n-well / p-well implants + anneal
  → STI: pad oxide/nitride, trench etch, liner, oxide fill, CMP
  → Gate oxide (IL + high-k), gate electrode (poly or dummy gate), gate patterning
  → LDD/extension + halo implants (NMOS, PMOS separately)
  → Spacer deposition and etch
  → Deep S/D implants (or SiGe/SiC epitaxy) + spike/laser anneal
  → (Gate-last: remove dummy gate → high-k/metal gate fill → CMP)
  → Silicide (NiSi) → contact etch stop, ILD, W contacts
  → Cu/low-k multilevel interconnect (damascene) → passivation, pads

Front-end steps (wells to silicide) build transistors at high temperature; back-end steps (contacts upward) must stay below ~400 °C. Separate masks dope NMOS and PMOS regions. Gate-last (replacement metal gate) avoids exposing the work-function metals to the high-temperature S/D anneal.

Yield, cost per die and chiplets

import math
# Die yield (Poisson and Murphy), gross dies, cost per good die, and chiplet advantage
D0 = 0.1                                                   # defects per cm^2
wafer_cost, D_mm = 10000.0, 300
def gross(area_mm2):
    return math.pi * (D_mm / 2) ** 2 / area_mm2 - math.pi * D_mm / math.sqrt(2 * area_mm2)
for area in (50, 200, 600):
    A = area / 100
    y_p = math.exp(-D0 * A)
    y_m = ((1 - math.exp(-D0 * A)) / (D0 * A)) ** 2
    good = gross(area) * y_m
    print(f"die {area:3d} mm^2: gross {gross(area):5.0f}, yield Poisson {y_p:.2f} / Murphy {y_m:.2f}, good {good:5.0f}, cost ${wafer_cost/good:7.2f}")
y_big = ((1 - math.exp(-D0 * 6)) / (D0 * 6)) ** 2
y_small = ((1 - math.exp(-D0 * 1.5)) / (D0 * 1.5)) ** 2
print(f"one 600 mm^2 die yield {y_big:.2f} vs four 150 mm^2 chiplets each {y_small:.2f} (known-good-die tested before assembly)")
# die  50 mm^2: gross  1319, yield Poisson 0.95 / Murphy 0.95, good  1255, cost $   7.97
# die 200 mm^2: gross   306, yield Poisson 0.82 / Murphy 0.82, good   252, cost $  39.74
# die 600 mm^2: gross    91, yield Poisson 0.55 / Murphy 0.57, good    51, cost $ 195.18
# one 600 mm^2 die yield 0.57 vs four 150 mm^2 chiplets each 0.86 (known-good-die tested before assembly)

With 0.1 defects/cm², a 50 mm² die yields 95% and costs ~$8 from a $10 000 wafer, but a 600 mm² die yields only ~57% and costs ~$195 — 24× more for 12× the area. Splitting it into four 150 mm² chiplets, each tested before assembly, raises per-chiplet yield to ~86%, the economic case for chiplet architectures (at the cost of packaging and interconnect overhead).

Common mistakes

Applications

Key takeaways

Going further