Operational Amplifier Fundamentals & Non-Idealities

The most useful analog building block. Learn the ideal op-amp and its two golden rules, the internal architecture (differential input, gain stage, output stage, compensation), negative feedback and the virtual short, then every real limitation that shows up on a datasheet: finite open-loop gain, gain-bandwidth product, slew rate and full-power bandwidth, input offset voltage and drift, input bias and offset current, CMRR and PSRR, input and output voltage range (rail-to-rail), output current and capacitive-load drive, noise, and op-amp families (bipolar, JFET, CMOS, chopper, current-feedback) — with Python quantifying gain error, bandwidth, slew limits and DC errors.

An op-amp is a very-high-gain differential amplifier designed to be used with negative feedback. Feedback components — not the op-amp's own wildly variable gain — then set the circuit's behaviour precisely.

Knowing the ideal model lets you design quickly; knowing the non-idealities lets you choose the right part and predict the real errors.

An analogy

An op-amp with feedback is like a hugely strong but blind servant who only knows 'push' or 'pull' — you give it a sensor (feedback network) that compares where the load is with where you want it, and it works tirelessly until the difference is zero.

The ideal op-amp

An ideal op-amp has:

AC limitations

Most op-amps are internally compensated with a single dominant pole: A_OL falls 20 dB/decade from a few Hz until it reaches 1 at the GBW (unity-gain frequency). Closed-loop bandwidth ≈ GBW/noise gain. Slew rate — the maximum dV/dt, set by the current available to charge the compensation capacitor — limits large, fast signals; exceeding it produces triangular distortion. Settling time, phase margin and output impedance (rising with frequency) matter for ADC drivers and capacitive loads.

DC errors

Input offset voltage V_OS (µV for precision/chopper, mV for general-purpose) and its drift (µV/°C) are amplified by the noise gain. Input bias current I_B (pA for CMOS/JFET, nA for bipolar) flows through source and feedback resistances; balancing impedances converts I_B error to the smaller I_OS error. Finite CMRR and PSRR convert common-mode and supply changes into input-referred errors.

Choosing an op-amp

Match the technology to the job: bipolar (low V_OS, low voltage noise, higher I_B), JFET (low I_B, audio), CMOS (pA I_B, rail-to-rail, low power, more 1/f noise), zero-drift/chopper (µV V_OS, sensors), current-feedback (very high slew, video), fully differential (ADC drivers). Check supply range, input common-mode range (including whether inputs work near the rails), output swing under load, noise density, GBW vs power, and stability with the actual load capacitance.

Formulas

Worked example: Finite gain error

Given: A_OL = 10⁴, ideal gain 100

Find: Actual gain.

Answer: 99.01 (1% low)

Worked example: Full-power bandwidth

Given: SR 13 V/µs, 10 V peak

Find: f_FPBW.

Answer: ≈ 207 kHz

Worked example: Offset at output

Given: V_OS 5 mV, noise gain 21

Find: Output offset.

Answer: 105 mV

Inside a classic op-amp

  v+ ──┐                           Cc (Miller compensation)
       │ Differential   ──►  High-gain  ──┬─||─┐  ──►  Class-AB   ──► v_out
  v− ──┘ input pair          stage (VAS)  └────┘       output stage
        (sets V_OS, I_B,     (most of A_OL)            (drive current,
         CMRR, noise)                                   swing to rails)

Three stages: a differential pair (input characteristics), a voltage-gain stage (most of the ~100 dB gain) with a Miller capacitor that creates the dominant pole for stability, and a push-pull output stage for low output impedance and current drive.

Quantifying op-amp non-idealities

import math
# Op-amp non-idealities: finite gain, GBW, slew rate, offset and bias current errors
A0, GBW, SR = 1e5, 1e6, 0.5e6          # open-loop gain, Hz, V/s
for G in (1, 10, 100):
    beta = 1 / G
    closed = A0 / (1 + A0 * beta)
    print(f"ideal gain {G:3d}: actual {closed:.4f} (error {(G-closed)/G*100:.3f}%), bandwidth {GBW/G/1e3:.0f} kHz")
Vp = 10.0
print(f"full-power bandwidth for 10 V peak: {SR/(2*math.pi*Vp)/1e3:.2f} kHz")
# Offset and bias currents in a gain-of-100 non-inverting amplifier (R1 = 1k, Rf = 99k)
Vos, Ib, Ios = 2e-3, 50e-9, 5e-9
R1, Rf = 1e3, 99e3
G = 1 + Rf / R1
out_vos = Vos * G
out_ib_unbal = Ib * Rf
Rp = R1 * Rf / (R1 + Rf)
out_ib_bal = Ios * Rf
print(f"output error from Vos: {out_vos*1e3:.0f} mV; from Ib (no compensation): {out_ib_unbal*1e3:.2f} mV; with Rp = {Rp:.0f} ohm: {out_ib_bal*1e3:.3f} mV")
print(f"CMRR 90 dB with 1 V common-mode change -> input-referred error {1/10**(90/20)*1e6:.1f} uV")
# ideal gain   1: actual 1.0000 (error 0.001%), bandwidth 1000 kHz
# ideal gain  10: actual 9.9990 (error 0.010%), bandwidth 100 kHz
# ideal gain 100: actual 99.9001 (error 0.100%), bandwidth 10 kHz
# full-power bandwidth for 10 V peak: 7.96 kHz
# output error from Vos: 200 mV; from Ib (no compensation): 4.95 mV; with Rp = 990 ohm: 0.495 mV
# CMRR 90 dB with 1 V common-mode change -> input-referred error 31.6 uV

With A_OL = 100 dB, a gain of 100 is only 0.1% low — but the bandwidth drops to 10 kHz (GBW 1 MHz). Slew rate limits a 10 V-peak sine to under 8 kHz, well below the small-signal bandwidth. A 2 mV offset becomes 200 mV at the output of a ×100 stage — often the dominant DC error — while matching the input resistances cuts bias-current error tenfold.

Common mistakes

Applications

Key takeaways

Going further