Current Sources & Current Mirrors

Precise, stable currents for biasing and active loads. Learn ideal vs real current sources, output resistance and compliance, the basic BJT and MOS mirrors, β error and base-current compensation, emitter degeneration, the Widlar source for tiny currents, Wilson and cascode mirrors for high output resistance, current ratios by device scaling, mismatch and layout, and discrete current sources (transistor + zener/LED references, JFET and LM334) — with Python computing mirror errors, Widlar resistors and output resistances.

Analog ICs are built from currents rather than resistors: current sources bias every stage, act as high-resistance loads for high gain, and set tail currents for differential pairs. A current mirror copies a reference current to one or many outputs.

The quality of a current source is judged by accuracy (copy ratio), output resistance (how little the current changes with output voltage), compliance (voltage range) and noise.

An analogy

A current mirror is like a copying machine for flow: one pipe's flow sets a pressure on a shared control line, and every other identical pipe connected to that line carries the same flow — regardless (almost) of what's downstream.

What makes a good current source

An ideal current source delivers a fixed current regardless of the voltage across it (infinite output resistance). Real sources have finite R_out (current changes with voltage) and need a minimum voltage (compliance) to stay in the active/saturation region. A resistor from a high voltage is a crude current source; transistors do far better.

Mirror variants

Common circuits:

Ratios and multiple outputs

Scaling emitter area (BJT) or W/L (MOS) scales the current: a 1:4 mirror delivers 4× I_REF. One reference can feed many outputs (bias distribution in ICs). Using unit devices in parallel, rather than one big device, gives the most accurate ratios.

Errors and discrete practice

Errors come from V_BE/V_TH mismatch, β, Early effect (V_CE of reference vs output differs), temperature gradients and noise. In discrete designs, matched dual transistors (same package) plus emitter resistors dropping 100–200 mV give reasonable mirrors; otherwise use a transistor with a stable base reference (zener, LED, TL431) and an emitter resistor, a JFET with source resistor, or ICs like the LM334/REF200. Supply-independent references (V_BE-referenced, bandgap) set I_REF in ICs.

Formulas

Worked example: β error

Given: Basic mirror, β = 50, I_REF 1 mA

Find: I_OUT.

Answer: 0.962 mA (−3.8%)

Worked example: Widlar resistor

Given: I_REF 1 mA, I_OUT 5 µA

Find: R_E.

Answer: ≈ 27.4 kΩ

Worked example: Ratio mirror

Given: MOS mirror, (W/L)₂ = 3(W/L)₁, I_REF 20 µA

Find: I_OUT (ignoring λ).

Answer: 60 µA

Basic, Widlar and cascode mirrors

  Basic BJT mirror          Widlar                 MOS cascode mirror
   +V                        +V                     I_REF      I_OUT
   R_ref   I_OUT             R_ref  I_OUT             │          │
   ├──┐     │                ├──┐    │               M3 ─┬──── M4
   │  Q1 ──Q2                │  Q1 ──Q2              │   (gates tied)
   └──┘     │                └──┘    R_E             M1 ─┬──── M2
   GND     GND               GND     GND             GND        GND

Q1 is diode-connected so its V_BE is set by I_REF; Q2 has the same V_BE and therefore (if matched) the same current. Widlar inserts R_E to make I_OUT much smaller than I_REF with modest resistors. Cascoding (M3/M4) shields M2 from output voltage changes, multiplying R_out by g_m r_o.

Mirror accuracy, Widlar design and output resistance

import math
# Current mirrors: basic BJT mirror with beta error, Widlar, output resistance, MOS mirror
VCC, VBE, beta, VA, VT = 12.0, 0.7, 100, 100.0, 0.02585
Rref = (VCC - VBE) / 1e-3
Iref = (VCC - VBE) / Rref
Iout = Iref / (1 + 2 / beta)
print(f"basic mirror: Rref = {Rref/1e3:.1f}k, Iref = {Iref*1e3:.3f} mA, Iout = {Iout*1e3:.4f} mA ({(Iout/Iref-1)*100:.2f}% beta error)")
print(f"with base-current helper: Iout = {Iref/(1+2/(beta*(beta+1)))*1e3:.5f} mA")
print(f"output resistance ro = VA/Iout = {VA/Iout/1e3:.0f}k; at Vout change of 5 V current changes {5/(VA/Iout)*1e6:.1f} uA")
# Widlar source: 10 uA from 1 mA reference -> RE = VT ln(Iref/Iout)/Iout
Io = 10e-6
RE = VT * math.log(1e-3 / Io) / Io
print(f"Widlar: RE = {RE/1e3:.2f}k for 10 uA (a basic mirror would need Rref = {(VCC-VBE)/Io/1e6:.2f} Mohm)")
gm_o = Io / VT
ro_o = VA / Io
print(f"Widlar Rout ~ ro*(1 + gm*RE) = {ro_o*(1+gm_o*RE)/1e6:.0f} Mohm")
# Cascode MOS mirror output resistance
gm, ro = 1e-3, 200e3
print(f"MOS mirror Rout = ro = {ro/1e3:.0f}k; cascode mirror Rout ~ gm*ro^2 = {gm*ro*ro/1e6:.0f} Mohm")
# Mismatch: 2 mV VBE mismatch -> current ratio error
print(f"2 mV VBE mismatch -> current mismatch {(math.exp(0.002/VT)-1)*100:.1f}%")
# basic mirror: Rref = 11.3k, Iref = 1.000 mA, Iout = 0.9804 mA (-1.96% beta error)
# with base-current helper: Iout = 0.99980 mA
# output resistance ro = VA/Iout = 102k; at Vout change of 5 V current changes 49.0 uA
# Widlar: RE = 11.90k for 10 uA (a basic mirror would need Rref = 1.13 Mohm)
# Widlar Rout ~ ro*(1 + gm*RE) = 56 Mohm
# MOS mirror Rout = ro = 200k; cascode mirror Rout ~ gm*ro^2 = 40 Mohm
# 2 mV VBE mismatch -> current mismatch 8.0%

The basic mirror loses 2% to base currents at β = 100; a β-helper transistor cuts that to 0.02%. Its 102 kΩ output resistance lets the current drift 49 µA over a 5 V swing — degeneration (Widlar) or cascoding raise R_out to tens of MΩ. A mere 2 mV V_BE mismatch gives 8% current error, which is why matched, common-centroid layout matters.

Common mistakes

Applications

Key takeaways

Going further