VLSI Design

From transistors to tape-out. How integrated circuits are designed: CMOS technology, digital and analog IC design, RTL with Verilog, SystemVerilog verification, FPGAs, synthesis and the ASIC flow, static timing analysis, physical design, and design for testability.

• CMOS Technology — CMOS is the technology behind nearly all digital chips. Learn NMOS/PMOS switches, the CMOS inverter and its voltage-transfer curve, static CMOS gates (pull-up/pull-down networks), switching delay, dynamic and leakage power, fabrication steps, and scaling from micrometres to FinFET and gate-all-around nodes.
• Digital IC Design — How digital chips are designed: specification, architecture, RTL, verification, synthesis, physical design and sign-off. Learn standard cells and libraries, design metrics (performance, power, area — PPA), gate-count and area estimation, clocking, low-power techniques and the front-end/back-end split.
• Analog IC Design — Designing amplifiers, references and converters on silicon. Learn the gm/I_D methodology, intrinsic gain, current mirrors, differential pairs, two-stage op-amps and compensation, bandgap references, device matching (Pelgrom), noise (thermal, flicker, kT/C), and layout techniques.
• RTL Design with Verilog — Register-transfer level design describes hardware as registers and the logic between them. Learn Verilog modules, ports, wires and regs, continuous vs procedural assignments, blocking vs non-blocking, combinational and sequential always blocks, finite state machines, parameters, testbenches, and synthesisable coding rules.
• SystemVerilog & Verification — Verification takes more than half of chip-design effort. Learn SystemVerilog design enhancements (logic, always_ff/always_comb, interfaces, structs), verification features (classes, constrained-random stimulus, functional coverage, assertions/SVA), UVM testbench architecture, and formal verification basics.
• FPGA Design — FPGAs are reconfigurable chips made of logic blocks, memories and DSP slices connected by programmable routing. Learn LUTs and flip-flops, CLBs, block RAM, DSP slices, clocking (PLLs/MMCMs), the FPGA flow (synthesis, implementation, bitstream), timing constraints, resource estimation, and SoC FPGAs.
• ASIC Flow & Logic Synthesis — From RTL to gates for a custom chip. Learn what logic synthesis does (translation, optimisation, technology mapping), SDC constraints, synthesis reports (area, timing, power), gate-level netlists and equivalence checking, ASIC vs FPGA economics (NRE vs unit cost), and foundry/PDK concepts.
• Static Timing Analysis — Static timing analysis (STA) verifies that every path meets timing without simulation. Learn timing paths, arrival and required times, setup and hold checks and slack, clock skew, jitter and uncertainty, false and multicycle paths, PVT corners and OCV, and how to fix violations.
• Physical Design — Turning a netlist into manufacturable layout. Learn floorplanning, power planning and IR drop, placement and utilisation, clock-tree synthesis, routing and congestion, wire delay (Elmore), parasitic extraction, physical verification (DRC, LVS, antenna), yield and dies per wafer.
• Design for Testability (DFT) — Manufactured chips must be tested for defects. Learn fault models (stuck-at, transition, bridging), controllability and observability, scan chains and scan insertion, ATPG and fault coverage, test time and compression, memory BIST and logic BIST, JTAG boundary scan (IEEE 1149.1), and defect level (DPPM).