ASIC Flow & Logic Synthesis

From RTL to gates for a custom chip. Learn what logic synthesis does (translation, optimisation, technology mapping), SDC constraints, synthesis reports (area, timing, power), gate-level netlists and equivalence checking, ASIC vs FPGA economics (NRE vs unit cost), and foundry/PDK concepts.

ASICs deliver the best performance and power per unit for high-volume products, at the cost of large up-front engineering and mask expenses. Synthesis is the step that turns RTL into a netlist of real library cells.

An analogy

Synthesis is like translating a recipe (RTL) into a shopping list and cooking plan using only ingredients from a specific supermarket (the standard-cell library).

What synthesis does

Translates RTL into generic logic, optimises (constant propagation, resource sharing, retiming), then maps to standard cells meeting timing, area and power targets.

Constraints and reports

SDC defines clocks, uncertainty, I/O delays, false and multicycle paths, loads and drives. Reports show worst slack, area by hierarchy and estimated power. Equivalence checking (LEC/Formality) proves the netlist matches RTL.

ASIC economics

Mask sets cost from tens of thousands (older nodes) to tens of millions of dollars (3–5 nm). ASICs win at high volume; FPGAs win at low volume or when flexibility is needed. Structured ASICs and multi-project wafers lower entry cost.

PDKs and corners

The foundry PDK provides device models, design rules, parasitic extraction decks and cell libraries. Designs are checked at process–voltage–temperature (PVT) corners and with on-chip variation (OCV/POCV) margins.

Formulas

Worked example: Break-even

Given: FPGA $50/unit; ASIC NRE $2M + $5/unit

Find: Break-even volume.

Answer: ≈ 44 000 units

Worked example: Clock constraint

Given: Target 500 MHz

Find: SDC period.

Answer: 2.0 ns period (plus uncertainty margin)

Synthesis script (Design Compiler-style Tcl)

set_app_var target_library   "slow_1v0_125c.db"
set_app_var link_library     "* slow_1v0_125c.db"

analyze  -format sverilog { rtl/top.sv rtl/alu.sv rtl/regfile.sv }
elaborate top
link

# Constraints: 500 MHz clock with 50 ps uncertainty
create_clock -name clk -period 2.0 [get_ports clk]
set_clock_uncertainty 0.05 [get_clocks clk]
set_input_delay  0.4 -clock clk [remove_from_collection [all_inputs] [get_ports clk]]
set_output_delay 0.4 -clock clk [all_outputs]
set_load 0.01 [all_outputs]

compile_ultra -gate_clock          ;# optimise + insert clock gating
report_timing -max_paths 10 > reports/timing.rpt
report_area                      > reports/area.rpt
report_power                     > reports/power.rpt
write -format verilog -hierarchy -output netlist/top_syn.v
write_sdc netlist/top.sdc

Synthesis reads RTL, applies constraints, optimises logic and maps it to library cells at a chosen PVT corner, then writes a gate-level netlist and constraints for place-and-route.

Common mistakes

Applications

Key takeaways

Going further