Static Timing Analysis

Static timing analysis (STA) verifies that every path meets timing without simulation. Learn timing paths, arrival and required times, setup and hold checks and slack, clock skew, jitter and uncertainty, false and multicycle paths, PVT corners and OCV, and how to fix violations.

A chip may have hundreds of millions of timing paths; simulating them all is impossible. STA computes worst-case delays through every path using cell and wire delay models, and reports slack — the margin by which each path meets (or fails) its requirement.

An analogy

STA is like checking every train connection in a timetable: each train (signal) must arrive at the station (flip-flop) before the next departure (clock edge), with enough time to board (setup).

Timing paths

Input → register, register → register, register → output, input → output. Each path has a launch edge, data path and capture edge.

Setup and hold

Setup: data must arrive before the next capture edge (max delay). Hold: data must not change too soon after the capture edge (min delay). Positive skew helps setup but hurts hold.

Exceptions

False paths (never exercised functionally, e.g. static configuration), multicycle paths (allowed several cycles), clock-domain crossings (handled by synchronisers, not STA).

Corners and variation

Analyse slow corners for setup and fast corners for hold, across voltage and temperature. On-chip variation derates, AOCV/POCV statistical models, SI (crosstalk) delay effects. Fix setup with upsizing, restructuring, pipelining or useful skew; fix hold by inserting delay buffers.

Formulas

• Setup slack: slack = (T + t_skew − t_su − t_unc) − (t_cq + t_comb,max)
• Hold slack: slack = (t_cq + t_comb,min) − (t_h + t_skew)
• Multicycle: Required time extended by N periods for N-cycle paths

Worked example: Setup slack

Given: T 1000 ps, t_cq 50, t_comb 800, t_su 40, skew −20 ps

Find: Slack.

• Required = 1000 − 20 − 40 = 940
• Arrival = 50 + 800 = 850
• Slack = 90 ps

Answer: +90 ps (met)

Worked example: Hold slack

Given: t_cq 50, t_comb,min 30, t_h 20, skew +40 ps

Find: Hold slack.

• Arrival = 80; required = 20 + 40 = 60
• Slack = 20 ps

Answer: +20 ps (met, but little margin)

Common mistakes

• Wrong: Fixing setup only at slow corner and forgetting hold at fast corner. — Right: Check both across all corners.
• Wrong: Declaring real paths false to pass timing. — Right: Only functionally impossible paths are false.

Applications

• Sign-off: PrimeTime/Tempus multi-corner STA.
• FPGA timing: Vivado/Quartus timing reports.
• ECO fixing: Targeted fixes after routing.

Key takeaways

• Setup = max path; hold = min path.
• Slack ≥ 0 at every corner.
• Exceptions: false/multicycle paths.
• Fix setup by speeding logic; hold by adding delay.

Going further

• POCV: Statistical variation-aware timing.
• SI analysis: Crosstalk delta delays.
• Useful skew: Deliberate clock scheduling.