CMOS Technology

CMOS is the technology behind nearly all digital chips. Learn NMOS/PMOS switches, the CMOS inverter and its voltage-transfer curve, static CMOS gates (pull-up/pull-down networks), switching delay, dynamic and leakage power, fabrication steps, and scaling from micrometres to FinFET and gate-all-around nodes.

Complementary MOS pairs an NMOS pull-down with a PMOS pull-up, so one is always off and almost no static current flows. This simple idea, repeated tens of billions of times per chip, powers every CPU, GPU and phone SoC.

An analogy

A CMOS inverter is like a see-saw of two switches: when one closes, the other opens — so the output is always firmly connected to either power or ground, never both.

The CMOS inverter

Input low: PMOS on, NMOS off → output high. Input high: NMOS on, PMOS off → output low. The voltage-transfer curve switches sharply near V_DD/2, giving large noise margins.

Static CMOS gates

NAND: NMOS in series, PMOS in parallel; NOR: the opposite. Complex gates (AOI/OAI) implement functions in one stage. PMOS are made wider (≈ 2×) to balance weaker hole mobility.

Power

Dynamic switching power dominates in active logic; short-circuit power during transitions; leakage (subthreshold, gate) grows at advanced nodes. Techniques: clock gating, power gating, multi-V_t cells, DVFS.

Fabrication and scaling

Wafer processing: oxidation, lithography (EUV at ≤ 7 nm), etching, ion implantation, deposition, CMP and metallisation with 10–20 metal layers. Planar MOSFETs gave way to FinFETs (22/16 nm) and gate-all-around nanosheets (3/2 nm) to control short-channel leakage.

Formulas

• Inverter delay (RC): t_pd ≈ 0.69 R_eq C_L
• Dynamic power: P_dyn = α C V_DD² f
• Leakage power: P_leak = I_leak V_DD
• Dennard scaling (factor S): Dimensions, V ÷ S → area ÷ S², delay ÷ S, power density constant

Worked example: Gate delay

Given: R_eq = 10 kΩ, C_L = 10 fF

Find: t_pd.

• t_pd = 0.69 × 10⁴ × 10⁻¹⁴ = 69 ps

Answer: 69 ps

Worked example: Chip dynamic power

Given: C_total = 1 nF, α = 0.1, V_DD = 0.8 V, f = 2 GHz

Find: P_dyn.

• P = 0.1 × 10⁻⁹ × 0.64 × 2 × 10⁹ = 0.128 W

Answer: 128 mW

Common mistakes

• Wrong: Ignoring leakage at advanced nodes. — Right: Leakage can be 20–40 % of total power.
• Wrong: Equal NMOS/PMOS widths. — Right: Size PMOS ≈ 2× for symmetric rise/fall.

Applications

• Processors & SoCs: Billions of CMOS transistors.
• Image sensors: CMOS active-pixel sensors.
• Mixed-signal ICs: Analog and digital on one die.

Key takeaways

• NMOS pull-down + PMOS pull-up.
• t_pd ≈ 0.69RC.
• P = αCV²f + leakage.
• Scaling: planar → FinFET → GAA.

Going further

• Logical effort: Optimal gate sizing along paths.
• Power gating: Shutting off idle blocks.
• GAA transistors: Nanosheet devices at 3 nm and below.