Introduction to VHDL & Digital Design

VHDL (VHSIC Hardware Description Language; VHSIC = Very High Speed Integrated Circuit) is a language for describing, simulating, and synthesizing digital hardware.

1.1 What is VHDL?

VHDL (VHSIC Hardware Description Language; VHSIC = Very High Speed Integrated Circuit) is a language for describing, simulating, and synthesizing digital hardware. You don't write a program that runs step-by-step on a CPU — you describe circuits that operate concurrently.

VHDL is used to:

Model hardware behavior and structure.

Simulate designs before building them.

Synthesize descriptions into gates/FPGA configurations (bitstreams) or ASIC netlists.

Verify designs with testbenches.

Document hardware precisely.

1.2 Software vs hardware thinking

Software (C, Python) Hardware (VHDL) statements execute sequentially everything runs in parallel variables are memory locations signals are wires/registers time is implicit time and clocks are explicit loops run repeatedly loops (in synthesis) are unrolled into replicated hardware functions are called components are instantiated (copied in silicon) cost = CPU time cost = area, power, timing (clock frequency)

1.3 History

US Department of Defense VHSIC program starts VHDL developed by Intermetrics, IBM, Texas Instruments IEEE 1076-1987 — first standard

VHDL-93 — major revision (still common in legacy code) IEEE 1164 (std_logic) and later 1076.3 (numeric_std)

VHDL-2000/2002 — protected types, minor fixes VHDL-2008 — huge usability improvements (process(all), fixed/float packages, generics improvements)

VHDL-2019 — interfaces/mode views, conditional analysis, more

VHDL is strongly typed (Ada heritage), verbose but precise. Its main alternative is (System)Verilog; VHDL is popular in Europe, aerospace, defense, and FPGA design.

1.4 Digital logic refresher

Combinational logic: outputs depend only on current inputs (gates, multiplexers, adders).

Sequential logic: outputs depend on inputs and stored state (flip-flops, registers, counters, FSMs), usually synchronized by a clock.

Synchronous design: all state changes on a clock edge — the dominant methodology.

Number systems: binary, hexadecimal, two's complement, Gray code.

Boolean algebra, Karnaugh maps, De Morgan's laws.

1.5 Levels of abstraction

what it does (algorithms) processes, high-level statements RTL (Register Transfer Level) registers + logic between them clocked processes + concurrent logic — synthesizable standard interconnection of components instantiations, port maps primitives (AND, OR, FF) netlists after synthesis