Tools & the Design Flow

Waveform viewers: GTKWave, Surfer, simulator built-in viewers.

2.1 Simulators

free, open-source VHDL simulator (VHDL-93/2008/partial 2019) free, open-source, fast VHDL-2008/2019 simulator ModelSim / Questa (Siemens) industry standard; free starter editions with Intel/AMD tools Vivado Simulator (xsim) bundled with AMD/Xilinx Vivado Riviera-PRO / Active-HDL (Aldec)

Xcelium (Cadence), VCS (Synopsys) ASIC-grade commercial simulators EDA Playground browser-based (edaplayground.com)

Waveform viewers: GTKWave, Surfer, simulator built-in viewers.

2.2 Synthesis & implementation tools

AMD Vivado Xilinx 7-series, UltraScale, Zynq, Versal Intel Quartus Prime Altera Cyclone, Arria, Stratix, Agilex Lattice Radiant / Diamond Microchip Libero PolarFire, SmartFusion Efinity / Gowin EDA Efinix / Gowin FPGAs Yosys + GHDL plugin + nextpnr open-source flow (Lattice iCE40/ECP5, Gowin)

Synopsys Design Compiler / Cadence Genus

2.3 Installing an open-source toolchain

The OSS CAD Suite (YosysHQ) bundles GHDL, NVC, Yosys, nextpnr, GTKWave, SymbiYosys, and cocotb for all platforms.

# Linux
sudo apt install ghdl gtkwave
# macOS
brew install ghdl gtkwave   # or: brew install nvc
# Windows: MSYS2 → pacman -S mingw-w64-ucrt-x86_64-ghdl ; or the OSS CAD Suite (all-in-one)

2.4 The design flow

Specification
   ↓
RTL design (VHDL)  ←──────────┐
   ↓                          │
Functional simulation (testbench) — fix bugs
   ↓
Synthesis (RTL → netlist of LUTs/FFs/gates)
   ↓
Implementation: place & route (map to physical resources)
   ↓
Static timing analysis (does it meet the clock frequency?)
   ↓
Bitstream generation (FPGA) / GDSII (ASIC)
   ↓
Program device → in-system debugging (ILA / SignalTap)

2.5 Editors

VS Code with TerosHDL or VHDL-LS (rust_hdl) extension, Sigasi (commercial), Emacs vhdl-mode, Vim with vhdl_ls; vendor IDEs.