Low Power, Reliability & ASIC

33.1 Power

Dynamic power ∝ C·V²·f·activity: reduce toggling (clock enables, operand isolation), lower frequency, use BRAM/DSP efficiently.

Clock gating via vendor primitives (BUFGCE) or tool optimizations — not with LUT logic.

Power analysis: Vivado report_power, Quartus Power Analyzer, with simulation activity (SAIF/VCD).

33.2 Reliability & safety

Single event upsets (SEU): radiation flips bits in configuration memory/registers → TMR (triple modular redundancy), scrubbing, ECC on memories.

Safe FSMs (illegal state recovery, Hamming-encoded states).

Watchdogs, parity/CRC on data paths.

Standards: DO-254 (avionics), ISO 26262 (automotive), IEC 61508 — require rigorous requirements traceability, verification, and coding standards.

33.3 ASIC considerations

No initial values; explicit resets everywhere needed.

Technology libraries, DFT (scan chains, BIST), clock tree synthesis, power intent (UPF), gate-level simulation with SDF timing.

Open-source ASIC flows (OpenLane/OpenROAD, Sky130/GF180 PDKs) accept VHDL via GHDL+Yosys.

🧪 Part III Exercises

Rewrite your Part II ALU testbench using VHDL-2008 features: process(all), to_hstring, std.env.finish, external names.

Infer a 1K×16 single-port block RAM and a 256×8 ROM initialized from a hex file; confirm inference in the synthesis report.

Design a synchronous FIFO with almost-full/almost-empty flags; verify with a randomized self-checking testbench.

Implement a 16-tap FIR filter in Q1.15 fixed point; compare against a Python/NumPy reference using file I/O.

Pipeline a 32-bit multiplier-accumulator to reach a higher Fmax; report timing before/after.

Build an asynchronous FIFO with Gray-code pointers and 2-FF synchronizers; simulate two unrelated clocks.

Implement a UART receiver with 16× oversampling, and loop it back to the transmitter on an FPGA board.

Write an AXI4-Lite slave with four 32-bit registers (one read-only status register); verify with OSVVM or cocotbext-axi.

Create a VUnit project with at least five tests for your FIFO; run them in CI with GHDL.

Add PSL assertions to your FIFO (never write when full, never read when empty) and prove them with SymbiYosys.