Radiation Effects in Semiconductor Devices

Semiconductors in space, accelerators and nuclear environments — and on the ground. Learn radiation environments (trapped protons/electrons, solar particles, galactic cosmic rays, atmospheric neutrons, alpha particles from packaging), total ionising dose (oxide-trapped charge and interface traps → V_T shifts, leakage), displacement damage (lifetime and mobility degradation in bipolar, optoelectronic and solar devices), single-event effects (SEU, SET, SEL, SEB, SEGR), linear energy transfer and critical charge, and hardening (radiation-hardened processes, SOI, enclosed-layout transistors, guard rings, TMR, EDAC, latch-up current limiting) — with Python relating LET to collected charge, critical charge vs node, and TID sensitivity vs oxide thickness.

Energetic particles and photons ionise semiconductors and oxides, creating charge that shifts transistor behaviour over time (dose effects) or instantly flips bits and triggers destructive events (single-event effects).

Satellites, aircraft, particle detectors, medical equipment and even data centres at sea level must account for radiation in reliability.

An analogy

Total dose is like sunburn accumulating slowly over a summer; single-event effects are like being hit by a single hailstone — one strike can knock something over (bit flip) or, in the worst case, break it (latch-up, burnout).

Environments

Where radiation comes from:

Total dose and displacement damage

Holes generated in SiO₂ are trapped near the Si interface, shifting V_T negatively (NMOS leakage) and creating interface traps that degrade swing and mobility. Shallow-trench isolation edges form parasitic leakage paths. Bipolar devices suffer gain loss, including enhanced low-dose-rate sensitivity (ELDRS). Displacement damage from protons/neutrons reduces minority-carrier lifetime — critical for solar cells, optocouplers, image sensors and BJTs.

Single-event effects

SEU/MBU in SRAM, flip-flops and configuration memory (FPGAs); SETs in combinational logic and analog circuits; SEL in bulk CMOS (destructive without current limiting); SEB and SEGR in power MOSFETs and IGBTs under high voltage (derate V_DS to ~50–75% in space); SEFI (functional interrupts) in complex ICs. Characterised by heavy-ion and proton cross-section vs LET curves; neutron soft-error rates expressed in FIT/Mbit.

Hardening

By process: SOI (small sensitive volume, no latch-up), epitaxial substrates, hardened oxides. By design: enclosed-layout transistors (no STI edge leakage), guard rings, DICE/TMR flip-flops, temporal filtering, EDAC/ECC with scrubbing, watchdogs, current-limited power with latch-up detection. By system: shielding (effective for protons/electrons, not GCR), redundancy, derating. Component selection uses RHA (radiation hardness assured) parts, COTS with test data, and mission-specific radiation analysis.

Formulas

Worked example: Deposited charge

Given: LET 20 MeV·cm²/mg, 2 µm collection

Find: Charge.

Answer: 0.41 pC

Worked example: Critical charge

Given: Node 2 fF at 0.9 V

Find: Q_crit.

Answer: 1.8 fC

Worked example: SER

Given: 500 FIT/Mbit, 64 Mbit

Find: FIT.

Answer: 32 000 FIT (≈ one upset per 3.6 years)

Radiation effects map

  Cumulative                              Single-event (one particle)
  TID: holes trapped in oxides,           SEU: bit flip in latch/SRAM (soft error)
       interface traps → V_T shift,       SET: transient glitch propagates in logic
       leakage (STI edges)                SEL: parasitic PNPN latches (destructive without current limit)
  DD:  lattice displacement →             SEB/SEGR: burnout/gate rupture in power MOSFETs
       lifetime ↓ (BJTs, solar, LEDs)     MBU: multiple bits flipped by one strike

Ionisation in oxides accumulates trapped positive charge and interface traps (TID). Non-ionising energy loss displaces atoms, creating recombination centres (displacement damage). A single heavy ion or neutron-induced secondary deposits a dense charge track; if a sensitive node collects more than its critical charge, the circuit misbehaves.

LET, critical charge and TID sensitivity

import math
# Single-event upset: charge deposited vs critical charge; TID threshold shift vs oxide thickness
for LET in (1, 10, 37, 60):
    Q_per_um = LET / 97.0                  # pC/um in Si (LET in MeV*cm^2/mg; 97 -> 1 pC/um)
    Q = Q_per_um * 1.0                     # 1 um collection depth
    print(f"LET {LET:2d} MeV*cm^2/mg: {Q*1e3:.0f} fC collected in 1 um")
for node, C, V in (("180 nm", 10e-15, 1.8), ("28 nm", 1.5e-15, 1.0), ("7 nm", 0.5e-15, 0.75)):
    Qc = C * V
    print(f"{node:6s} SRAM node: Qcrit ~ C*V = {Qc*1e15:.2f} fC -> upset threshold LET ~ {Qc*1e12*97:.2f} MeV*cm^2/mg")
for tox_nm in (100, 20, 5):
    print(f"TID: oxide {tox_nm:3d} nm -> relative threshold shift ~ (tox)^2 = {(tox_nm/100)**2:.4f} x that of 100 nm")
# LET  1 MeV*cm^2/mg: 10 fC collected in 1 um
# LET 10 MeV*cm^2/mg: 103 fC collected in 1 um
# LET 37 MeV*cm^2/mg: 381 fC collected in 1 um
# LET 60 MeV*cm^2/mg: 619 fC collected in 1 um
# 180 nm SRAM node: Qcrit ~ C*V = 18.00 fC -> upset threshold LET ~ 1.75 MeV*cm^2/mg
# 28 nm  SRAM node: Qcrit ~ C*V = 1.50 fC -> upset threshold LET ~ 0.15 MeV*cm^2/mg
# 7 nm   SRAM node: Qcrit ~ C*V = 0.38 fC -> upset threshold LET ~ 0.04 MeV*cm^2/mg
# TID: oxide 100 nm -> relative threshold shift ~ (tox)^2 = 1.0000 x that of 100 nm
# TID: oxide  20 nm -> relative threshold shift ~ (tox)^2 = 0.0400 x that of 100 nm
# TID: oxide   5 nm -> relative threshold shift ~ (tox)^2 = 0.0025 x that of 100 nm

An ion with LET 37 MeV·cm²/mg deposits ~380 fC in 1 µm of silicon — hundreds of times more than a modern SRAM node needs to flip (critical charge ~1 fC at 28 nm). Shrinking nodes lower Q_crit (more sensitive per bit) while smaller collection volumes partly compensate. Thin modern gate oxides are much less sensitive to TID (∝ t_ox²), so field and isolation oxides dominate dose effects in advanced CMOS.

Common mistakes

Applications

Key takeaways

Going further