Emerging Devices: TFETs, 2-D FETs, ReRAM, PCM, MRAM & Neuromorphic
What might come next — and how mature it really is. For each technology — tunnel FETs, 2-D material FETs (MoS₂, WSe₂) and graphene devices, nanowire/GAA extensions, memristors and resistive RAM, phase-change memory, spin-transfer and spin-orbit-torque MRAM, ferroelectric FETs/FeRAM, spintronic logic concepts, neuromorphic and in-memory computing devices, single-electron transistors, quantum-device concepts and molecular electronics — learn structure, operating principle, potential advantage, main limitation and research/application status (from production to research-only), without overstating maturity — with Python comparing subthreshold swings, MRAM TMR, PCM windows, crossbar sneak paths and 2-D channel scale length.
Conventional CMOS faces limits in switching energy (60 mV/dec), scaling (atomic dimensions), memory bandwidth (the 'memory wall') and volatility. Many new devices attack one of these limits — but most trade one problem for another.
Engineers must judge technologies by evidence: some (MRAM, PCM, FeRAM, GAA) are in products; others (TFETs, 2-D logic, molecular electronics) remain research topics.
An analogy
Emerging devices are like prototype vehicles: electric cars went from concept to mainstream, flying cars remain demonstrations. Each prototype solves a real problem, but only some overcome cost, reliability and manufacturing hurdles.
Beyond-CMOS logic
Candidates and status:
- Tunnel FETs — S < 60 mV/dec shown at low current; on-current too low → research
- 2-D material FETs (MoS₂, WSe₂) — excellent electrostatics; contacts, doping, wafer-scale growth → research/pilot
- Graphene — very high mobility but no bandgap → poor logic switch; RF/sensor/interconnect research
- Negative-capacitance FETs — ferroelectric gate stacks; mixed evidence
- Spintronic logic, single-electron transistors, molecular electronics → research concepts
Emerging memories
STT-MRAM: non-volatile, fast, high endurance — in production as embedded NVM (replacing eFlash at 22 nm and below) and last-level cache candidates; SOT-MRAM faster, research/early products. PCM: multi-level, byte-addressable storage-class memory (commercialised then discontinued in some product lines), used in embedded and neuromorphic research. ReRAM: simple, CMOS-compatible, embedded products exist; variability and endurance are challenges. FeRAM/FeFET: HfO₂-based ferroelectrics revived FeRAM with CMOS-compatible materials — products (FeRAM) and development (FeFET).
Neuromorphic and in-memory computing
Resistive crossbars perform matrix-vector multiplication in place (Ohm's and Kirchhoff's laws), promising large energy savings for neural-network inference. Challenges: device variability, drift, limited precision, ADC overhead, selectors and endurance. Digital neuromorphic chips (spiking) exist in research platforms; analogue in-memory computing is in advanced research and early prototypes.
Quantum devices
Semiconductor spin qubits in Si/SiGe quantum dots, single-electron transistors as charge sensors, and cryogenic CMOS control electronics reuse semiconductor fabrication for quantum computing. They operate near millikelvin temperatures and are research-stage technologies; superconducting and trapped-ion qubits are currently more advanced systems.
Formulas
- Boltzmann limit:
S ≥ (kT/q) ln 10 ≈ 60 mV/dec (MOSFET) - TMR:
TMR = (R_AP − R_P)/R_P - Crossbar sneak paths:
≈ (N − 1)² parallel paths for an N×N passive array - 2-D scale length:
λ = √((ε_ch/ε_ox)t_ch t_ox) — sub-nm bodies - Memristor state:
V = R(w)·I, dw/dt = f(I) (history-dependent)
Worked example: Gate swing saved
Given: 6 decades, S 60 vs 40 mV/dec
Find: Voltage difference.
- 6 × (60 − 40)
Answer: 120 mV
Worked example: TMR
Given: R_P 3 kΩ, R_AP 7.5 kΩ
Find: TMR.
- (7.5 − 3)/3
Answer: 150%
Worked example: Sneak paths
Given: 32 × 32 passive array
Find: Approximate paths.
- 31²
Answer: 961
Operating principles at a glance
TFET: p⁺ source │ gated intrinsic channel │ n⁺ drain → band-to-band tunnelling filters hot carriers → S < 60
2-D FET: monolayer MoS₂ channel (0.65 nm) → ultimate electrostatic control; contacts & growth are hard
ReRAM: metal / oxide (HfO₂) / metal → conductive filament forms (SET) and ruptures (RESET)
PCM: GST alloy amorphous (high R) ⇄ crystalline (low R) by current-pulse heating
MRAM: MTJ (CoFeB/MgO/CoFeB) parallel = low R, antiparallel = high R; STT/SOT switching
FeFET: ferroelectric HfZrO gate → non-volatile V_T shiftEach device changes a different physical state: carrier injection mechanism (TFET), channel thickness (2-D), atomic filaments (ReRAM), crystal phase (PCM), magnetisation (MRAM) or ferroelectric polarisation (FeFET). The state change defines speed, energy, endurance and retention.
Swing, TMR, PCM window, sneak paths and 2-D scale length
import math
# Emerging devices: TFET vs MOSFET swing, MRAM TMR, PCM resistance window, crossbar sneak currents
VT = 0.02585
print(f"MOSFET swing limit at 300 K: {VT*math.log(10)*1e3:.1f} mV/dec; TFET demos: 20-50 mV/dec at low current")
for S in (60, 30):
print(f"swing {S} mV/dec: 5 decades of current need {5*S} mV of gate swing")
Rp, Rap = 2e3, 5e3
print(f"MRAM MTJ: TMR = (Rap-Rp)/Rp = {(Rap-Rp)/Rp*100:.0f}%; read at 0.1 V: {0.1/Rp*1e6:.0f} uA vs {0.1/Rap*1e6:.0f} uA")
Rset, Rreset = 10e3, 1e6
print(f"PCM: SET {Rset/1e3:.0f} kohm (crystalline) vs RESET {Rreset/1e6:.0f} Mohm (amorphous) -> window {Rreset/Rset:.0f}x")
N = 64
print(f"{N}x{N} passive crossbar reading one high-R cell: ~{(N-1)**2} parallel sneak paths -> selectors (1S1R) needed")
eps_r, t_body, t_ox = 7.0, 0.65, 1.0 # monolayer MoS2 ~0.65 nm
lam = math.sqrt(eps_r / 3.9 * t_body * t_ox)
print(f"monolayer MoS2 FET natural length ~ {lam:.2f} nm (vs ~1.9 nm Si GAA) -> ultimate gate-length scaling")
# MOSFET swing limit at 300 K: 59.5 mV/dec; TFET demos: 20-50 mV/dec at low current
# swing 60 mV/dec: 5 decades of current need 300 mV of gate swing
# swing 30 mV/dec: 5 decades of current need 150 mV of gate swing
# MRAM MTJ: TMR = (Rap-Rp)/Rp = 150%; read at 0.1 V: 50 uA vs 20 uA
# PCM: SET 10 kohm (crystalline) vs RESET 1 Mohm (amorphous) -> window 100x
# 64x64 passive crossbar reading one high-R cell: ~3969 parallel sneak paths -> selectors (1S1R) needed
# monolayer MoS2 FET natural length ~ 1.08 nm (vs ~1.9 nm Si GAA) -> ultimate gate-length scalingHalving the swing to 30 mV/dec would allow the same on/off ratio with half the gate swing — the promise of TFETs (limited in practice by low on-current). An MTJ with 150% TMR gives a clear 50 vs 20 µA read difference. PCM offers ~100× resistance windows (multi-level storage). Passive 64 × 64 crossbars suffer thousands of sneak paths, so selectors are required. A monolayer MoS₂ channel's ~1 nm scale length is why 2-D materials are studied for the ultimate transistor.
Common mistakes
- Wrong: Presenting research devices as ready replacements for CMOS. — Right: State maturity and limitations explicitly.
- Wrong: Judging a device by one figure of merit. — Right: Consider I_on, variability, endurance, integration, cost.
- Wrong: Using graphene as a logic switch. — Right: No bandgap → poor off state.
Applications
- Embedded NVM: MRAM/ReRAM in MCUs.
- AI accelerators: In-memory computing research.
- Storage-class memory: PCM-based persistent memory.
- Quantum computing: Si spin qubits, cryo-CMOS.
Key takeaways
- Each device targets a CMOS limit: swing, scaling, memory wall, volatility.
- MRAM, ReRAM, PCM, FeRAM are in (niche) production.
- TFET, 2-D logic, molecular devices remain research.
- Judge by evidence: I_on, variability, endurance, cost.
Going further
- Negative-capacitance FETs: Ferroelectric voltage amplification.
- Spin-orbit torque MRAM: Separate read/write paths.
- Analog in-memory computing: Accuracy vs energy.