Analog IC Design: OTAs, Two-Stage Op-Amps & gm/ID Sizing

How the amplifiers inside chips are designed. Learn the CMOS design flow (specs → topology → sizing → simulation → layout → verification), the 5-transistor OTA, telescopic and folded-cascode OTAs, the two-stage Miller-compensated op-amp and its pole-splitting/RHP-zero, gm/ID methodology across weak, moderate and strong inversion, bias circuits and current references, common-mode feedback in fully differential amplifiers, matching and layout (common-centroid, interdigitation, dummies, guard rings), corners and Monte Carlo, and IC-level noise, offset and PSRR — with Python sizing a 5T OTA and a two-stage Miller op-amp for ~60° phase margin.

Integrated analog design has different rules from board design: transistors are cheap and match well, resistors and capacitors are expensive and imprecise in absolute value, and every node has parasitic capacitance. Designers build gain from transistors, bias from mirrors and accuracy from ratios.

The operational transconductance amplifier (OTA) — a voltage-in, current-out amplifier loaded by capacitance — is the core block of switched-capacitor circuits, filters, ADCs and regulators.

An analogy

Designing an analog IC is like designing a small city where every building (transistor) is identical and cheap, but land (area) and power are limited: you get precision by making neighbourhoods symmetrical (matching), not by making each building perfect.

OTA topologies

Common choices:

gm/ID design methodology

Rather than trusting square-law equations (invalid in modern short-channel processes), designers simulate g_m/I_D, f_T and intrinsic gain g_m·r_o versus g_m/I_D for several lengths, then pick an inversion level: weak inversion (high g_m/I_D ≈ 20–25, low power, slow), moderate inversion (balanced), strong inversion (low g_m/I_D ≈ 5–10, fast, more linear). Given required g_m and chosen g_m/I_D, current follows; given current density I_D/W from the charts, width follows.

Fully differential design and CMFB

Fully differential amplifiers double swing, cancel even harmonics and reject supply/substrate noise — standard in ADCs. Because the output common-mode is undefined by differential feedback, a common-mode feedback loop senses the average output (resistive or switched-capacitor sensing) and adjusts a bias current. The CMFB loop needs its own stability analysis.

Layout, matching and verification

Offset and gain accuracy depend on matching: use large devices for critical pairs (Pelgrom's law), common-centroid and interdigitated placement to cancel gradients, dummy devices at array ends, identical orientation and surroundings, guard rings against substrate noise, and careful routing of sensitive nodes. Verify with process corners (TT/FF/SS/FS/SF), temperature, supply variation and Monte Carlo mismatch, plus post-layout parasitic extraction.

Formulas

Worked example: Transconductance

Given: I_D 100 µA, V_OV 0.15 V

Find: g_m.

Answer: 1.33 mS

Worked example: GBW

Given: g_m 1.33 mS, C_L 2 pF

Find: GBW of a 5T OTA.

Answer: ≈ 106 MHz

Worked example: Slew rate

Given: I_tail 20 µA, C_L 2 pF

Find: SR.

Answer: 10 V/µs

Five-transistor OTA

          V_DD
     M3 ─┬──┬─ M4        (PMOS current-mirror load)
         │  └────────── v_out ──┬── C_L
     M1 ─┘      M2 ─────┘       GND
  v_in+ ┤        ├ v_in−
         └──┬───┘
           M5 (tail current source, I_tail)
           GND

The NMOS differential pair M1/M2 converts differential voltage into current; the PMOS mirror M3/M4 copies M1's current to the output so both halves contribute, giving single-ended output with gain g_m1(r_o2 ∥ r_o4). The dominant pole is at the output node with C_L.

Sizing a 5T OTA and a two-stage Miller op-amp

import math
# CMOS OTA sizing: 5-transistor OTA and two-stage Miller op-amp (square-law estimates)
Itail, VOV, lam, CL = 20e-6, 0.2, 0.1, 2e-12       # lambda per volt for chosen L
gm1 = (Itail / 2) * 2 / VOV
ro = 1 / (lam * Itail / 2)
A0 = gm1 * ro / 2                                   # gm1 * (ro2 || ro4)
GBW = gm1 / (2 * math.pi * CL)
SR = Itail / CL
print(f"5T OTA: gm1 = {gm1*1e6:.0f} uS, ro = {ro/1e6:.1f} Mohm, A0 = {A0:.0f} ({20*math.log10(A0):.1f} dB)")
print(f"GBW = {GBW/1e6:.2f} MHz, slew rate = {SR/1e6:.0f} V/us")
# Two-stage Miller op-amp: second stage gm6 = 10*gm1 and Cc = 0.22*CL for ~60 deg PM
gm6, Cc = 10 * gm1, 0.22 * 10e-12
CL2 = 10e-12
GBW2 = gm1 / (2 * math.pi * Cc)
p2 = gm6 / (2 * math.pi * CL2)
z = gm6 / (2 * math.pi * Cc)
PM = 90 - math.degrees(math.atan(GBW2 / p2)) - math.degrees(math.atan(GBW2 / z))
print(f"two-stage: GBW = {GBW2/1e6:.2f} MHz, p2 = {p2/1e6:.1f} MHz, RHP zero = {z/1e6:.0f} MHz, PM ~ {PM:.0f} deg")
print(f"gm/ID = {gm1/(Itail/2):.0f} 1/V (moderate inversion ~10-15, weak ~20-25)")
# 5T OTA: gm1 = 100 uS, ro = 1.0 Mohm, A0 = 50 (34.0 dB)
# GBW = 7.96 MHz, slew rate = 10 V/us
# two-stage: GBW = 7.23 MHz, p2 = 15.9 MHz, RHP zero = 72 MHz, PM ~ 60 deg
# gm/ID = 10 1/V (moderate inversion ~10-15, weak ~20-25)

With 20 µA of tail current and 0.2 V overdrive the 5T OTA gives only 34 dB but a respectable 8 MHz GBW into 2 pF. Adding a second gain stage with g_m6 = 10·g_m1 and C_c = 0.22·C_L yields ~7 MHz GBW into 10 pF with about 60° phase margin — the classic textbook trade-off. g_m/I_D = 10 V⁻¹ places the input pair in moderate inversion.

Common mistakes

Applications

Key takeaways

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